| Line 62... |
Line 62... |
reg [7:0] X;
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reg [7:0] X;
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reg [7:0] Y;
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reg [7:0] Y;
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reg [7:0] STATUS;
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reg [7:0] STATUS;
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reg [7:0] result;
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reg [7:0] result;
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reg [7:0] bcd1;
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reg [7:0] op1;
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reg [7:0] bcd2;
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reg [7:0] op2;
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`include "t6507lp_package.v"
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`include "t6507lp_package.v"
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or negedge reset_n)
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begin
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begin
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if (reset_n == 0) begin
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if (reset_n == 0) begin
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//$display("RESTART");
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alu_result <= 0;
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alu_result <= 0;
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alu_status[C] <= 0;
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alu_status[C] <= 0;
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alu_status[N] <= 0;
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alu_status[N] <= 0;
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alu_status[V] <= 0;
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alu_status[V] <= 0;
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alu_status[5] <= 1;
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alu_status[5] <= 1;
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| Line 87... |
Line 86... |
Y <= 0;
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Y <= 0;
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alu_x <= 0;
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alu_x <= 0;
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alu_y <= 0;
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alu_y <= 0;
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end
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end
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else if ( alu_enable == 1 ) begin
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else if ( alu_enable == 1 ) begin
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//$display("A = %h result = %h", A, result);
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//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
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case (alu_opcode)
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case (alu_opcode)
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
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ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
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ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
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EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
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EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
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ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
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ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
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SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
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SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
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LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
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LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
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begin
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begin
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//$display("A = %h result = %h", A, result);
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//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
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A <= result;
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A <= result;
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alu_result <= result;
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alu_result <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
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LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
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| Line 190... |
Line 184... |
endcase
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endcase
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end
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end
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end
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end
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always @ (*) begin
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always @ (*) begin
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bcd1 = A;
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op1 = A;
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bcd2 = alu_a;
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op2 = alu_a;
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result = alu_result;
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result = alu_result;
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STATUS[N] = alu_status[N];
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STATUS[N] = alu_status[N];
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STATUS[C] = alu_status[C];
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STATUS[C] = alu_status[C];
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STATUS[V] = alu_status[V];
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STATUS[V] = alu_status[V];
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STATUS[B] = alu_status[B];
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STATUS[B] = alu_status[B];
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| Line 225... |
Line 219... |
CLD_IMP: begin
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CLD_IMP: begin
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STATUS[D] = 1'b0;
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STATUS[D] = 1'b0;
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end
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end
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// CLI - Clear Interrupt Disable
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// CLI - Clear Interrupt Disable
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// TODO: verify if this should be supported by 6507
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CLI_IMP: begin
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CLI_IMP: begin
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STATUS[I] = 1'b0;
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STATUS[I] = 1'b0;
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end
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end
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// CLV - Clear Overflow Flag
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// CLV - Clear Overflow Flag
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| Line 315... |
Line 308... |
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// ADC - Add with carry
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// ADC - Add with carry
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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if (alu_status[D] == 1) begin
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if (alu_status[D] == 1) begin
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if (A[3:0] > 9) begin
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if (A[3:0] > 9) begin
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bcd1 = A + 6; // A = A - 10 and A = A + 16
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op1 = A + 6; // A = A - 10 and A = A + 16
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end
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end
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if (bcd1[7:4] > 9) begin
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if (op1[7:4] > 9) begin
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bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16
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op1 = op1[7:4] + 6; // A = A - 10 and A = A + 16
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end
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end
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if (alu_a[3:0] > 9) begin
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if (alu_a[3:0] > 9) begin
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bcd2 = alu_a + 6;
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op2 = alu_a + 6;
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end
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end
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if (bcd2[7:4] > 9) begin
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if (op2[7:4] > 9) begin
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bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16
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op2 = op2[7:4] + 6; // A = A - 10 and A = A + 16
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end
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end
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end
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end
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//$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
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{STATUS[C],result} = op1 + op2 + alu_status[C];
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//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
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if ((op1[7] == op2[7]) && (op1[7] != result[7]))
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{STATUS[C],result} = bcd1 + bcd2 + alu_status[C];
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if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))
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STATUS[V] = 1;
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STATUS[V] = 1;
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else
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else
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STATUS[V] = 0;
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STATUS[V] = 0;
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if (alu_status[D] == 1) begin
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if (alu_status[D] == 1) begin
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| Line 344... |
Line 335... |
if (result[7:4] > 9) begin
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if (result[7:4] > 9) begin
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result = result[7:4] + 6; // A = A - 10 and A = A + 16
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result = result[7:4] + 6; // A = A - 10 and A = A + 16
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STATUS[C] = 1;
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STATUS[C] = 1;
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end
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end
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end
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end
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//$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
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//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
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end
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end
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// AND - Logical AND
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// AND - Logical AND
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
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result = A & alu_a;
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result = A & alu_a;
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| Line 384... |
Line 373... |
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// SBC - Subtract with Carry
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// SBC - Subtract with Carry
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SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
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SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
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if (alu_status[D] == 1) begin
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if (alu_status[D] == 1) begin
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if (A[3:0] > 9) begin
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if (A[3:0] > 9) begin
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bcd1 = A + 6; // A = A - 10 and A = A + 16
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op1 = A + 6; // A = A - 10 and A = A + 16
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end
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end
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if (bcd1[7:4] > 9) begin
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if (op1[7:4] > 9) begin
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bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16
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op1 = op1[7:4] + 6; // A = A - 10 and A = A + 16
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end
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end
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if (alu_a[3:0] > 9) begin
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if (alu_a[3:0] > 9) begin
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bcd2 = alu_a + 6;
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op2 = alu_a + 6;
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end
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end
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if (bcd2[7:4] > 9) begin
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if (op2[7:4] > 9) begin
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bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16
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op2 = op2[7:4] + 6; // A = A - 10 and A = A + 16
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end
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end
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end
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end
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{STATUS[C],result} = bcd1 - bcd2 - ~alu_status[C];
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{STATUS[C],result} = op1 - op2 - ~alu_status[C];
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if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))
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if ((op1[7] == op2[7]) && (op1[7] != result[7]))
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STATUS[V] = 1;
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STATUS[V] = 1;
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else
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else
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STATUS[V] = 0;
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STATUS[V] = 0;
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end
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end
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| Line 426... |
Line 416... |
{result,STATUS[C]} = {1'b0,alu_a};
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{result,STATUS[C]} = {1'b0,alu_a};
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end
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end
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// ROL - Rotate Left
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// ROL - Rotate Left
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ROL_ACC : begin
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ROL_ACC : begin
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{STATUS[C],result} = {A,alu_status[C]}; //TODO: does it really work?
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{STATUS[C],result} = {A,alu_status[C]};
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end
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end
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ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
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ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
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{STATUS[C],result} = {alu_a,alu_status[C]};
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{STATUS[C],result} = {alu_a,alu_status[C]};
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end
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end
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