| Line 64... |
Line 64... |
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reg [7:0] STATUS;
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reg [7:0] STATUS;
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reg [7:0] result;
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reg [7:0] result;
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reg [7:0] op1;
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reg [7:0] op1;
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reg [7:0] op2;
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reg [7:0] op2;
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reg [7:0] bcdl;
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reg [7:0] bcdh;
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`include "t6507lp_package.v"
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`include "t6507lp_package.v"
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or negedge reset_n)
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begin
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begin
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| Line 315... |
Line 318... |
end
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end
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// ADC - Add with carry
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// ADC - Add with carry
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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if (alu_status[D] == 1) begin
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if (alu_status[D] == 1) begin
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if (A[3:0] > 9) begin
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bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
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op1 = A + 6; // A = A - 10 and A = A + 16
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bcdh = A[7:4] + alu_a[7:4];
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end
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if (bcdl > 9) begin
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if (op1[7:4] > 9) begin
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bcdl = bcdl - 10; // A = A - 10 and A = A + 16
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op1 = op1[7:4] + 6; // A = A - 10 and A = A + 16
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bcdh = bcdh + 1; // A = A - 10 and A = A + 16
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end
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if (alu_a[3:0] > 9) begin
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op2 = alu_a + 6;
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end
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end
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if (op2[7:4] > 9) begin
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if (bcdh > 9) begin
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op2 = op2[7:4] + 6; // A = A - 10 and A = A + 16
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STATUS[C] = 1;
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bcdh = bcdh - 10;
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end
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end
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/*if (op1[7:4] > 9) begin
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op1 = op1[7:4] + 6; // A = A - 10 and A = A + 16
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end
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if (alu_a[3:0] > 9) begin
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op2 = alu_a + 6;
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end
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if (op2[7:4] > 9) begin
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op2 = op2[7:4] + 6; // A = A - 10 and A = A + 16
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end
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*/
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result = {bcdh[3:0],bcdl[3:0]};
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end
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end
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else begin
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{STATUS[C],result} = op1 + op2 + alu_status[C];
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{STATUS[C],result} = op1 + op2 + alu_status[C];
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end
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if ((op1[7] == op2[7]) && (op1[7] != result[7]))
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if ((op1[7] == op2[7]) && (op1[7] != result[7]))
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STATUS[V] = 1;
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STATUS[V] = 1;
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else
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else
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STATUS[V] = 0;
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STATUS[V] = 0;
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//$display("op1 + op2 + C = result + C (V)");
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//$display("op1 + op2 + C = result + C (V)");
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//$display("%d + %d + %b = %d + %b (%b)", op1, op2, alu_status[C],result,STATUS[C],STATUS[V]);
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//$display("%d + %d + %b = %d + %b (%b)", op1, op2, alu_status[C],result,STATUS[C],STATUS[V]);
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/*
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if (alu_status[D] == 1) begin
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if (alu_status[D] == 1) begin
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if (result[3:0] > 9) begin
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if (result[3:0] > 9) begin
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result = result[3:0] + 6; // A = A - 10 and A = A + 16
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result = result[3:0] + 6; // A = A - 10 and A = A + 16
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end
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end
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if (result[7:4] > 9) begin
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if (result[7:4] > 9) begin
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result = result[7:4] + 6; // A = A - 10 and A = A + 16
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result = result[7:4] + 6; // A = A - 10 and A = A + 16
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STATUS[C] = 1;
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STATUS[C] = 1;
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end
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end
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end
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end
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*/
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end
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end
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// AND - Logical AND
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// AND - Logical AND
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
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result = A & alu_a;
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result = A & alu_a;
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| Line 384... |
Line 399... |
end
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end
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// SBC - Subtract with Carry
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// SBC - Subtract with Carry
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SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
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SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
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if (alu_status[D] == 1) begin
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if (alu_status[D] == 1) begin
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if (A[3:0] > 9) begin
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bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
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op1 = A + 6; // A = A - 10 and A = A + 16
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bcdh = A[7:4] + alu_a[7:4];
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end
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if (bcdl > 9) begin
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if (op1[7:4] > 9) begin
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bcdl = bcdl - 10; // A = A - 10 and A = A + 16
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op1 = op1[7:4] + 6; // A = A - 10 and A = A + 16
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bcdh = bcdh + 1; // A = A - 10 and A = A + 16
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end
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if (alu_a[3:0] > 9) begin
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op2 = alu_a + 6;
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end
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end
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if (op2[7:4] > 9) begin
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if (bcdh > 9) begin
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op2 = op2[7:4] + 6; // A = A - 10 and A = A + 16
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STATUS[C] = 1;
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bcdh = bcdh - 10;
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end
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end
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result = {bcdh[3:0],bcdl[3:0]};
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end
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end
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else begin
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{STATUS[C],result} = op1 - op2 - ~alu_status[C];
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{STATUS[C],result} = op1 - op2 - ~alu_status[C];
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end
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if ((op1[7] == op2[7]) && (op1[7] != result[7]))
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if ((op1[7] == op2[7]) && (op1[7] != result[7]))
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STATUS[V] = 1;
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STATUS[V] = 1;
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else
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else
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STATUS[V] = 0;
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STATUS[V] = 0;
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end
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end
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