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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 163 and 164
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| Rev 163 |
Rev 164 |
| Line 66... |
Line 66... |
reg [7:0] result;
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reg [7:0] result;
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reg [7:0] op1;
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reg [7:0] op1;
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reg [7:0] op2;
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reg [7:0] op2;
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reg [7:0] bcdl;
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reg [7:0] bcdl;
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reg [7:0] bcdh;
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reg [7:0] bcdh;
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reg [7:0] bcdh2;
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reg [7:0] AL;
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reg [7:0] AH;
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`include "t6507lp_package.v"
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`include "t6507lp_package.v"
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or negedge reset_n)
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begin
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begin
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| Line 319... |
Line 321... |
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// ADC - Add with carry
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// ADC - Add with carry
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// TODO: verify synthesis for % operand
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// TODO: verify synthesis for % operand
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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if (alu_status[D] == 1) begin
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if (alu_status[D] == 1) begin
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bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
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AL = A[3:0] + alu_a[3:0] + alu_status[C];
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bcdh = A[7:4] + alu_a[7:4];
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AH = A[7:4] + alu_a[7:4];
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if (bcdl > 9) begin
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if (AL > 9) begin
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bcdh = bcdh + bcdl[5:4];
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bcdh = AH + (AL / 10);
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bcdl = bcdl % 10;
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bcdl = AL % 10;
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end
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end
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if (bcdh > 9) begin
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if (AH > 9) begin
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STATUS[C] = 1;
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STATUS[C] = 1;
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bcdh = bcdh % 10;
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bcdh2 = bcdh % 10;
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end
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end
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result = {bcdh[3:0],bcdl[3:0]};
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result = {bcdh2[3:0],bcdl[3:0]};
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end
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end
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else
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else
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{STATUS[C],result} = op1 + op2 + alu_status[C];
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{STATUS[C],result} = op1 + op2 + alu_status[C];
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if ((op1[7] == op2[7]) && (op1[7] != result[7]))
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if ((op1[7] == op2[7]) && (op1[7] != result[7]))
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