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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 164 and 165

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Rev 164 Rev 165
Line 122... Line 122...
                                Y          <= result;
                                Y          <= result;
                                alu_y      <= result;
                                alu_y      <= result;
                                alu_status <= STATUS;
                                alu_status <= STATUS;
                        end
                        end
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
                        CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS, PHP_IMP :
                        CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :
                        begin
                        begin
                                alu_status <= STATUS;
                                alu_status <= STATUS;
                        end
                        end
                        PHA_IMP :
                        PHA_IMP :
                        begin
                        begin
Line 185... Line 185...
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
                        begin
                        begin
                                alu_result <= result;
                                alu_result <= result;
                                alu_status <= STATUS;
                                alu_status <= STATUS;
                        end
                        end
 
                        PHP_IMP : begin
 
                        end
                        default : begin
                        default : begin
                                //$display("ERROR");
                                //$display("ERROR");
                        end
                        end
                endcase
                endcase
        end
        end
Line 321... Line 323...
 
 
                // ADC - Add with carry
                // ADC - Add with carry
                // TODO: verify synthesis for % operand
                // TODO: verify synthesis for % operand
                ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
                ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
                        if (alu_status[D] == 1) begin
                        if (alu_status[D] == 1) begin
 
                                $display("MODO DECIMAL");
                                AL = A[3:0] + alu_a[3:0] + alu_status[C];
                                AL = A[3:0] + alu_a[3:0] + alu_status[C];
                                AH = A[7:4] + alu_a[7:4];
                                AH = A[7:4] + alu_a[7:4];
 
                                $display("AL = %h", AL);
 
                                $display("AH = %h", AH);
                                if (AL > 9) begin
                                if (AL > 9) begin
                                        bcdh = AH + (AL / 10);
                                        bcdh = AH + (AL / 10);
                                        bcdl = AL % 10;
                                        bcdl = AL % 10;
                                end
                                end
                                if (AH > 9) begin
                                if (AH > 9) begin
                                        STATUS[C] = 1;
                                        STATUS[C] = 1;
                                        bcdh2 = bcdh % 10;
                                        bcdh2 = bcdh % 10;
                                end
                                end
 
                                $display("bcdh = %h", bcdh);
 
                                $display("bcdl = %h", bcdl);
                                result = {bcdh2[3:0],bcdl[3:0]};
                                result = {bcdh2[3:0],bcdl[3:0]};
 
                                $display("result = %h", result);
                        end
                        end
                        else
                        else begin
 
                                $display("MODO NORMAL");
                                {STATUS[C],result} = op1 + op2 + alu_status[C];
                                {STATUS[C],result} = op1 + op2 + alu_status[C];
 
                        end
 
 
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                                STATUS[V] = 1;
                        else
                        else
                                STATUS[V] = 0;
                                STATUS[V] = 0;
Line 432... Line 442...
                                        bcdh = bcdh % 10;
                                        bcdh = bcdh % 10;
                                end
                                end
                                result = {bcdh[3:0],bcdl[3:0]};
                                result = {bcdh[3:0],bcdl[3:0]};
                        end
                        end
                        else
                        else
                                {STATUS[C],result} = op1 - op2 - ~alu_status[C];
                                {STATUS[C],result} = op1 - op2 - ( 1 - alu_status[C]);
 
 
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                                STATUS[V] = 1;
                        else
                        else
                                STATUS[V] = 0;
                                STATUS[V] = 0;

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