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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 166 and 167

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Rev 166 Rev 167
Line 429... Line 429...
                                STATUS[V] = 1;
                                STATUS[V] = 1;
                        else
                        else
                                STATUS[V] = 0;
                                STATUS[V] = 0;
*/
*/
                        if (alu_status[D] == 1) begin
                        if (alu_status[D] == 1) begin
                                bcdl = A[3:0] - alu_a[3:0] - ~alu_status[C];
                                bcdl = A[3:0] - alu_a[3:0] - ( 1 - alu_status[C] );
                                bcdh = A[7:4] - alu_a[7:4];
                                bcdh = A[7:4] - alu_a[7:4];
                                if (bcdl > 9) begin
                                if (bcdl > 9) begin
                                        bcdh = bcdh + bcdl[5:4];
                                        bcdh = bcdh + bcdl[5:4];
                                        bcdl = bcdl % 10;
                                        bcdl = bcdl % 10;
                                end
                                end

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