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Line 323... |
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// ADC - Add with carry
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// ADC - Add with carry
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// TODO: verify synthesis for % operand
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// TODO: verify synthesis for % operand
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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if (alu_status[D] == 1) begin
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if (alu_status[D] == 1) begin
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<<<<<<< .mine
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<<<<<<< .mine
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bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
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bcdh = A[7:4] + alu_a[7:4];
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$write("1: bcdl %d bcdh %d\n", bcdl, bcdh);
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if (bcdl > 9) begin
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//$write("\n %d \n", bcdl[6:4]);
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bcdh = bcdh + bcdl[5:4];
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bcdl = bcdl % 10;
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=======
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=======
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$display("MODO DECIMAL");
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$display("MODO DECIMAL");
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>>>>>>> .r165
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AL = A[3:0] + alu_a[3:0] + alu_status[C];
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AL = A[3:0] + alu_a[3:0] + alu_status[C];
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AH = A[7:4] + alu_a[7:4];
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AH = A[7:4] + alu_a[7:4];
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$display("AL = %h", AL);
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$display("AL = %h", AL);
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$display("AH = %h", AH);
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$display("AH = %h", AH);
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if (AL > 9) begin
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if (AL > 9) begin
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bcdh = AH + (AL / 10);
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bcdh = AH + (AL / 10);
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bcdl = AL % 10;
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bcdl = AL % 10;
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>>>>>>> .r164
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end
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end
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if (AH > 9) begin
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if (AH > 9) begin
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STATUS[C] = 1;
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STATUS[C] = 1;
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bcdh2 = bcdh % 10;
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bcdh2 = bcdh % 10;
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end
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end
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<<<<<<< .mine
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<<<<<<< .mine
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//$write("bcdl %d bcdh %d\n", bcdl, bcdh);
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result = {bcdh[3:0],bcdl[3:0]};
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=======
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=======
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$display("bcdh = %h", bcdh);
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$display("bcdh = %h", bcdh);
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$display("bcdl = %h", bcdl);
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$display("bcdl = %h", bcdl);
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>>>>>>> .r165
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result = {bcdh2[3:0],bcdl[3:0]};
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result = {bcdh2[3:0],bcdl[3:0]};
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<<<<<<< .mine
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>>>>>>> .r164
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=======
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$display("result = %h", result);
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$display("result = %h", result);
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>>>>>>> .r165
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end
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end
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else begin
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else begin
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$display("MODO NORMAL");
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$display("MODO NORMAL");
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{STATUS[C],result} = op1 + op2 + alu_status[C];
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{STATUS[C],result} = op1 + op2 + alu_status[C];
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end
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end
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