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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 172 and 173

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Rev 172	Rev 173
Line 69...	Line 69...
`reg [7:0] bcdl;`	`reg [7:0] bcdl;`
`reg [7:0] bcdh;`	`reg [7:0] bcdh;`
`reg [7:0] bcdh2;`	`reg [7:0] bcdh2;`
`reg [7:0] AL;`	`reg [7:0] AL;`
`reg [7:0] AH;`	`reg [7:0] AH;`
	`reg C_aux;`
	`reg sign;`

`include "t6507lp_package.v"	`include "t6507lp_package.v"

`always @ (posedge clk or negedge reset_n)`	`always @ (posedge clk or negedge reset_n)`
`begin`	`begin`
Line 171...	Line 173...
`alu_status[I] <= STATUS[I];`	`alu_status[I] <= STATUS[I];`
`alu_status[D] <= STATUS[D];`	`alu_status[D] <= STATUS[D];`
`alu_status[B] <= STATUS[B];`	`alu_status[B] <= STATUS[B];`
`alu_status[V] <= STATUS[V];`	`alu_status[V] <= STATUS[V];`
`alu_status[N] <= STATUS[N];`	`alu_status[N] <= STATUS[N];`
	`alu_status[5] <= 1;`
`end`	`end`
`BIT_ZPG, BIT_ABS :`	`BIT_ZPG, BIT_ABS :`
`begin`	`begin`
`alu_status[Z] <= STATUS[Z];`	`alu_status[Z] <= STATUS[Z];`
`alu_status[V] <= alu_a[6];`	`alu_status[V] <= alu_a[6];`
Line 185...	Line 188...
`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :`	`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :`
`begin`	`begin`
`alu_result <= result;`	`alu_result <= result;`
`alu_status <= STATUS;`	`alu_status <= STATUS;`
`end`	`end`
`PHP_IMP : begin`	`//PHP_IMP : begin`
`end`	`//end`
`default : begin`	`default : begin`
`//$display("ERROR");`	`//$display("ERROR");`
`end`	`end`
`endcase`	`endcase`
`end`	`end`
Line 213...	Line 216...
`bcdl = 0;`	`bcdl = 0;`
`bcdh = 0;`	`bcdh = 0;`
`bcdh2 = 0;`	`bcdh2 = 0;`
`AL = 0;`	`AL = 0;`
`AH = 0;`	`AH = 0;`
	`sign = op2[7];`

`case (alu_opcode)`	`case (alu_opcode)`
`// BIT - Bit Test`	`// BIT - Bit Test`
`BIT_ZPG, BIT_ABS: begin`	`BIT_ZPG, BIT_ABS: begin`
`result = A & alu_a;`	`result = A & alu_a;`
Line 446...	Line 449...
`STATUS[V] = 1;`	`STATUS[V] = 1;`
`else`	`else`
`STATUS[V] = 0;`	`STATUS[V] = 0;`
`*/`	`*/`
`if (alu_status[D] == 1) begin`	`if (alu_status[D] == 1) begin`
`bcdl = A[3:0] - alu_a[3:0] - ~alu_status[C];`	`bcdl = A[3:0] - alu_a[3:0] - ( 1 - alu_status[C] );`
`bcdh = A[7:4] - alu_a[7:4];`	`bcdh = A[7:4] - alu_a[7:4];`
`if (bcdl > 9) begin`	`if (bcdl > 9) begin`
`bcdh = bcdh + bcdl[5:4];`	`bcdh = bcdh + bcdl[5:4];`
`bcdl = bcdl % 10;`	`bcdl = bcdl % 10;`
`end`	`end`
Line 458...	Line 461...
`STATUS[C] = 1;`	`STATUS[C] = 1;`
`bcdh = bcdh % 10;`	`bcdh = bcdh % 10;`
`end`	`end`
`result = {bcdh[3:0],bcdl[3:0]};`	`result = {bcdh[3:0],bcdl[3:0]};`
`end`	`end`
`else`	`else begin`
`{STATUS[C],result} = op1 - op2 - ( 1 - alu_status[C] );`	`op2 = ~alu_a;`
	`{C_aux,result} = op1 + op2 + alu_status[C];`
	`STATUS[C] = ~C_aux;`
	`end`

`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
	`if ((op1[7] == sign) && (op1[7] != result[7]))`
`STATUS[V] = 1;`	`STATUS[V] = 1;`
`else`	`else`
`STATUS[V] = 0;`	`STATUS[V] = 0;`

`end`	`end`

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 172 and 173