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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 174 and 175

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Rev 174	Rev 175
Line 166...	Line 166...
`begin`	`begin`
`alu_status[B] <= 1;`	`alu_status[B] <= 1;`
`end`	`end`
`PLP_IMP, RTI_IMP :`	`PLP_IMP, RTI_IMP :`
`begin`	`begin`
`alu_status[C] <= STATUS[C];`	`alu_status[C] <= alu_a[C];`
`alu_status[Z] <= STATUS[Z];`	`alu_status[Z] <= alu_a[Z];`
`alu_status[I] <= STATUS[I];`	`alu_status[I] <= alu_a[I];`
`alu_status[D] <= STATUS[D];`	`alu_status[D] <= alu_a[D];`
`alu_status[B] <= STATUS[B];`	`alu_status[B] <= alu_a[B];`
`alu_status[V] <= STATUS[V];`	`alu_status[V] <= alu_a[V];`
`alu_status[N] <= STATUS[N];`	`alu_status[N] <= alu_a[N];`
`alu_status[5] <= 1;`	`alu_status[5] <= 1;`
`end`	`end`
`BIT_ZPG, BIT_ABS :`	`BIT_ZPG, BIT_ABS :`
`begin`	`begin`
`alu_status[Z] <= STATUS[Z];`	`alu_status[Z] <= STATUS[Z];`
Line 198...	Line 198...
`endcase`	`endcase`
`end`	`end`
`end`	`end`

`always @ (*) begin`	`always @ (*) begin`
	`if (alu_enable == 1) begin`
`op1 = A;`	`op1 = A;`
`op2 = alu_a;`	`op2 = alu_a;`
`result = alu_result;`	`result = alu_result;`
`STATUS[N] = alu_status[N];`	`STATUS[N] = alu_status[N];`
`STATUS[C] = alu_status[C];`	`STATUS[C] = alu_status[C];`
Line 255...	Line 256...
`//NOP_IMP: begin`	`//NOP_IMP: begin`
`// Do nothing :-D`	`// Do nothing :-D`
`//end`	`//end`

`// PLP - Pull Processor Status Register`	`// PLP - Pull Processor Status Register`
	`// RTI - Return from Interrupt`
`PLP_IMP, RTI_IMP: begin`	`PLP_IMP, RTI_IMP: begin`
`STATUS = alu_a;`	`STATUS = alu_a;`
`end`	`end`

`PLA_IMP : begin`	`PLA_IMP : begin`
Line 490...	Line 492...
`end`	`end`
`endcase`	`endcase`
`STATUS[Z] = (result == 0) ? 1 : 0;`	`STATUS[Z] = (result == 0) ? 1 : 0;`
`STATUS[N] = result[7];`	`STATUS[N] = result[7];`
`end`	`end`
	`end`
`endmodule`	`endmodule`


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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 174 and 175