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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 176 and 178

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Rev 176	Rev 178
Line 128...	Line 128...
`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,`	`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,`
`CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :`	`CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :`
`begin`	`begin`
`alu_status <= STATUS;`	`alu_status <= STATUS;`
`end`	`end`
`PHA_IMP :`	`PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin`
`begin`
`alu_result <= result;`	`alu_result <= result;`
`end`	`end`
	`STX_ZPG, STX_ZPY, STX_ABS : begin`
	`alu_x <= result;`
	`end`
	`STY_ZPG, STY_ZPX, STY_ABS : begin`
	`alu_y <= result;`
	`end`
`SEC_IMP :`	`SEC_IMP :`
`begin`	`begin`
`alu_status[C] <= 1;`	`alu_status[C] <= 1;`
`end`	`end`
`SED_IMP :`	`SED_IMP :`
Line 410...	Line 415...
`result = A \| alu_a;`	`result = A \| alu_a;`
`end`	`end`

`// SBC - Subtract with Carry`	`// SBC - Subtract with Carry`
`SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin`	`SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin`
`op2 = ~alu_a;`
`if (alu_status[D] == 1) begin`	`if (alu_status[D] == 1) begin`
	`bcdl = op1[3:0] - op2[3:0] - (1 - alu_status[C]);`
`bcdl = op1[3:0] + op2[3:0] + alu_status[C];`	`bcdh = op1[7:4] - op2[7:4];`
`bcdh = op1[7:4] + op2[7:4];`
`if (bcdl > 9) begin`	`if (bcdl > 9) begin`
`bcdh = bcdh + bcdl[5:4];`	`bcdh = bcdh + bcdl[5:4];`
`bcdl = bcdl % 10;`	`bcdl = bcdl % 10;`
`end`	`end`
`if (bcdh > 9) begin`	`if (bcdh > 9) begin`
Line 426...	Line 429...
`bcdh = bcdh % 10;`	`bcdh = bcdh % 10;`
`end`	`end`
`result = {bcdh[3:0],bcdl[3:0]};`	`result = {bcdh[3:0],bcdl[3:0]};`
`end`	`end`
`else begin`	`else begin`
`{C_aux,result} = op1 + op2 + alu_status[C];`	`op2 = ~alu_a;`
	`result = op1 + op2 + alu_status[C];`
`STATUS[C] = ~result[7];`	`STATUS[C] = ~result[7];`
`end`	`end`


`if ((op1[7] == sign) && (op1[7] != result[7]))`	`if ((op1[7] == sign) && (op1[7] != result[7]))`

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 176 and 178