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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 178 and 179
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| Rev 178 |
Rev 179 |
| Line 416... |
Line 416... |
end
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end
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// SBC - Subtract with Carry
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// SBC - Subtract with Carry
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SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
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SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
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if (alu_status[D] == 1) begin
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if (alu_status[D] == 1) begin
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bcdl = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
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op2 = ~op2;
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bcdh = op1[7:4] - op2[7:4];
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AL = A[3:0] + alu_a[3:0] + alu_status[C];
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if (bcdl > 9) begin
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AH = A[7:4] + alu_a[7:4];
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bcdh = bcdh + bcdl[5:4];
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if (AL > 9) begin
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bcdl = bcdl % 10;
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bcdh = AH + (AL / 10);
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bcdl = AL % 10;
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end
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else begin
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bcdh = AH;
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bcdl = AL;
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end
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end
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if (bcdh > 9) begin
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if (bcdh > 9) begin
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STATUS[C] = 1;
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STATUS[C] = 1;
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bcdh = bcdh % 10;
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bcdh2 = bcdh % 10;
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end
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end
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result = {bcdh[3:0],bcdl[3:0]};
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else begin
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STATUS[C] = 0;
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bcdh2 = bcdh;
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end
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result = {bcdh2[3:0],bcdl[3:0]};
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end
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end
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else begin
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else begin
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op2 = ~alu_a;
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//$display("MODO NORMAL");
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result = op1 + op2 + alu_status[C];
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{STATUS[C],result} = op1 + op2 + alu_status[C];
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STATUS[C] = ~result[7];
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end
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end
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/* if (alu_status[D] == 1) begin
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bcdl = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
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bcdh = op1[7:4] - op2[7:4];
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if (bcdl > 9) begin
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bcdh = bcdh + bcdl[5:4];
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bcdl = bcdl % 10;
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end
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if (bcdh > 9) begin
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STATUS[C] = 1;
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bcdh = bcdh % 10;
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end
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result = {bcdh[3:0],bcdl[3:0]};
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end
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else begin
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op2 = ~alu_a;
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result = op1 + op2 + alu_status[C];
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STATUS[C] = ~result[7];
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end
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*/
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if ((op1[7] == sign) && (op1[7] != result[7]))
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if ((op1[7] == sign) && (op1[7] != result[7]))
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STATUS[V] = 1;
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STATUS[V] = 1;
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else
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else
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STATUS[V] = 0;
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STATUS[V] = 0;
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