| Line 56... |
Line 56... |
output reg [7:0] alu_result;
|
output reg [7:0] alu_result;
|
output reg [7:0] alu_status;
|
output reg [7:0] alu_status;
|
output reg [7:0] alu_x;
|
output reg [7:0] alu_x;
|
output reg [7:0] alu_y;
|
output reg [7:0] alu_y;
|
|
|
reg [7:0] A;
|
//reg [7:0] A;
|
reg [7:0] X;
|
//reg [7:0] X;
|
reg [7:0] Y;
|
//reg [7:0] Y;
|
|
|
reg [7:0] STATUS;
|
reg [7:0] STATUS;
|
reg [7:0] result;
|
reg [7:0] result;
|
reg [7:0] op1;
|
reg [7:0] op1;
|
reg [7:0] op2;
|
reg [7:0] op2;
|
reg [7:0] bcdl;
|
reg [7:0] bcdl;
|
reg [7:0] bcdh;
|
reg [7:0] bcdh;
|
reg [7:0] bcdh2;
|
reg [7:0] bcdh2;
|
reg [7:0] AL;
|
reg [7:0] AL;
|
reg [7:0] AH;
|
reg [7:0] AH;
|
reg C_aux;
|
//reg C_aux;
|
reg sign;
|
reg sign;
|
|
|
`include "t6507lp_package.v"
|
`include "t6507lp_package.v"
|
|
|
always @ (posedge clk or negedge reset_n)
|
always @ (posedge clk or negedge reset_n)
|
| Line 86... |
Line 86... |
alu_status[5] <= 1;
|
alu_status[5] <= 1;
|
alu_status[Z] <= 1;
|
alu_status[Z] <= 1;
|
alu_status[I] <= 0;
|
alu_status[I] <= 0;
|
alu_status[B] <= 0;
|
alu_status[B] <= 0;
|
alu_status[D] <= 0;
|
alu_status[D] <= 0;
|
A <= 0;
|
//A <= 0;
|
X <= 0;
|
//X <= 0;
|
Y <= 0;
|
//Y <= 0;
|
alu_x <= 0;
|
alu_x <= 0;
|
alu_y <= 0;
|
alu_y <= 0;
|
end
|
end
|
else if ( alu_enable == 1 ) begin
|
else if ( alu_enable == 1 ) begin
|
case (alu_opcode)
|
case (alu_opcode)
|
| Line 102... |
Line 102... |
EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
|
EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
|
ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
|
ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
|
SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
|
SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
|
LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
|
LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
|
begin
|
begin
|
A <= result;
|
//A <= result;
|
alu_result <= result;
|
alu_result <= result;
|
alu_status <= STATUS;
|
alu_status <= STATUS;
|
end
|
end
|
LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
|
LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
|
begin
|
begin
|
X <= result;
|
//X <= result;
|
alu_x <= result;
|
alu_x <= result;
|
alu_status <= STATUS;
|
alu_status <= STATUS;
|
end
|
end
|
TXS_IMP :
|
TXS_IMP :
|
begin
|
begin
|
X <= result;
|
//X <= result;
|
alu_x <= result;
|
alu_x <= result;
|
end
|
end
|
LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
|
LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
|
begin
|
begin
|
Y <= result;
|
//Y <= result;
|
alu_y <= result;
|
alu_y <= result;
|
alu_status <= STATUS;
|
alu_status <= STATUS;
|
end
|
end
|
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
|
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
|
CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :
|
CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :
|
| Line 204... |
Line 204... |
end
|
end
|
end
|
end
|
|
|
always @ (*) begin
|
always @ (*) begin
|
if (alu_enable == 1) begin
|
if (alu_enable == 1) begin
|
op1 = A;
|
//op1 = A;
|
|
op1 = alu_result;
|
op2 = alu_a;
|
op2 = alu_a;
|
result = alu_result;
|
result = alu_result;
|
STATUS[N] = alu_status[N];
|
STATUS[N] = alu_status[N];
|
STATUS[C] = alu_status[C];
|
STATUS[C] = alu_status[C];
|
STATUS[V] = alu_status[V];
|
STATUS[V] = alu_status[V];
|
STATUS[B] = alu_status[B];
|
STATUS[B] = alu_status[B];
|
STATUS[I] = alu_status[I];
|
STATUS[I] = alu_status[I];
|
STATUS[D] = alu_status[D];
|
STATUS[D] = alu_status[D];
|
STATUS[Z] = alu_status[Z];
|
STATUS[Z] = alu_status[Z];
|
STATUS[N] = alu_status[N];
|
|
STATUS[5] = 1;
|
STATUS[5] = 1;
|
|
|
bcdl = 0;
|
bcdl = 0;
|
bcdh = 0;
|
bcdh = 0;
|
bcdh2 = 0;
|
bcdh2 = 0;
|
| Line 227... |
Line 227... |
sign = op2[7];
|
sign = op2[7];
|
|
|
case (alu_opcode)
|
case (alu_opcode)
|
// BIT - Bit Test
|
// BIT - Bit Test
|
BIT_ZPG, BIT_ABS: begin
|
BIT_ZPG, BIT_ABS: begin
|
result = A & alu_a;
|
//result = A & alu_a;
|
|
result = alu_result & alu_a;
|
end
|
end
|
|
|
// BRK - Force Interrupt
|
// BRK - Force Interrupt
|
BRK_IMP: begin
|
//BRK_IMP: begin
|
STATUS[B] = 1'b1;
|
// STATUS[B] = 1'b1;
|
end
|
//end
|
|
|
// CLC - Clear Carry Flag
|
// CLC - Clear Carry Flag
|
CLC_IMP: begin
|
//CLC_IMP: begin
|
STATUS[C] = 1'b0;
|
// STATUS[C] = 1'b0;
|
end
|
//end
|
|
|
// CLD - Clear Decimal Flag
|
// CLD - Clear Decimal Flag
|
CLD_IMP: begin
|
//CLD_IMP: begin
|
STATUS[D] = 1'b0;
|
// STATUS[D] = 1'b0;
|
end
|
//end
|
|
|
// CLI - Clear Interrupt Disable
|
// CLI - Clear Interrupt Disable
|
CLI_IMP: begin
|
//CLI_IMP: begin
|
STATUS[I] = 1'b0;
|
// STATUS[I] = 1'b0;
|
end
|
//end
|
|
|
// CLV - Clear Overflow Flag
|
// CLV - Clear Overflow Flag
|
CLV_IMP: begin
|
//CLV_IMP: begin
|
STATUS[V] = 1'b0;
|
// STATUS[V] = 1'b0;
|
end
|
//end
|
|
|
// NOP - No Operation
|
// NOP - No Operation
|
//NOP_IMP: begin
|
//NOP_IMP: begin
|
// Do nothing :-D
|
// Do nothing :-D
|
//end
|
//end
|
| Line 275... |
Line 276... |
// STA - Store Accumulator
|
// STA - Store Accumulator
|
// PHA - Push A
|
// PHA - Push A
|
// TAX - Transfer Accumulator to X
|
// TAX - Transfer Accumulator to X
|
// TAY - Transfer Accumulator to Y
|
// TAY - Transfer Accumulator to Y
|
TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
|
TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
|
result = A;
|
//result = A;
|
|
result = alu_result;
|
end
|
end
|
|
|
// STX - Store X Register
|
// STX - Store X Register
|
// TXA - Transfer X to Accumulator
|
// TXA - Transfer X to Accumulator
|
// TXS - Transfer X to Stack pointer
|
// TXS - Transfer X to Stack pointer
|
STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
|
STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
|
result = X;
|
//result = X;
|
|
result = alu_x;
|
end
|
end
|
|
|
// STY - Store Y Register
|
// STY - Store Y Register
|
// TYA - Transfer Y to Accumulator
|
// TYA - Transfer Y to Accumulator
|
STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
|
STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
|
result = Y;
|
//result = Y;
|
|
result = alu_y;
|
end
|
end
|
|
|
// SEC - Set Carry Flag
|
// SEC - Set Carry Flag
|
SEC_IMP: begin
|
//SEC_IMP: begin
|
STATUS[C] = 1'b1;
|
// STATUS[C] = 1'b1;
|
end
|
//end
|
|
|
// SED - Set Decimal Flag
|
// SED - Set Decimal Flag
|
SED_IMP: begin
|
//SED_IMP: begin
|
STATUS[D] = 1'b1;
|
// STATUS[D] = 1'b1;
|
end
|
//end
|
|
|
// SEI - Set Interrupt Disable
|
// SEI - Set Interrupt Disable
|
SEI_IMP: begin
|
//SEI_IMP: begin
|
STATUS[I] = 1'b1;
|
// STATUS[I] = 1'b1;
|
end
|
//end
|
|
|
// INC - Increment memory
|
// INC - Increment memory
|
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
|
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
|
result = alu_a + 1;
|
result = alu_a + 1;
|
end
|
end
|
|
|
// INX - Increment X Register
|
// INX - Increment X Register
|
INX_IMP: begin
|
INX_IMP: begin
|
result = X + 1;
|
//result = X + 1;
|
|
result = alu_x + 1;
|
end
|
end
|
|
|
// INY - Increment Y Register
|
// INY - Increment Y Register
|
INY_IMP : begin
|
INY_IMP : begin
|
result = Y + 1;
|
//result = Y + 1;
|
|
result = alu_y + 1;
|
end
|
end
|
|
|
// DEC - Decrement memory
|
// DEC - Decrement memory
|
DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
|
DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
|
result = alu_a - 1;
|
result = alu_a - 1;
|
end
|
end
|
|
|
// DEX - Decrement X register
|
// DEX - Decrement X register
|
DEX_IMP: begin
|
DEX_IMP: begin
|
result = X - 1;
|
//result = X - 1;
|
|
result = alu_x - 1;
|
end
|
end
|
|
|
// DEY - Decrement Y Register
|
// DEY - Decrement Y Register
|
DEY_IMP: begin
|
DEY_IMP: begin
|
result = Y - 1;
|
//result = Y - 1;
|
|
result = alu_y - 1;
|
end
|
end
|
|
|
// ADC - Add with carry
|
// ADC - Add with carry
|
// TODO: verify synthesis for % operand
|
// TODO: verify synthesis for % operand
|
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
|
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
|
if (alu_status[D] == 1) begin
|
if (alu_status[D] == 1) begin
|
//$display("MODO DECIMAL");
|
//$display("MODO DECIMAL");
|
AL = A[3:0] + alu_a[3:0] + alu_status[C];
|
//AL = A[3:0] + alu_a[3:0] + alu_status[C];
|
AH = A[7:4] + alu_a[7:4];
|
AL = op1[3:0] + op2[3:0] + alu_status[C];
|
//$display("AL = %d", AL);
|
//AH = A[7:4] + alu_a[7:4];
|
//$display("AH = %d", AH);
|
AH = op1[7:4] + op2[7:4];
|
|
$display("AL = %d", AL);
|
|
$display("AH = %d", AH);
|
if (AL > 9) begin
|
if (AL > 9) begin
|
bcdh = AH + (AL / 10);
|
bcdh = AH + (AL / 10);
|
bcdl = AL % 10;
|
bcdl = AL % 10;
|
end
|
end
|
else begin
|
else begin
|
| Line 381... |
Line 391... |
STATUS[V] = 0;
|
STATUS[V] = 0;
|
end
|
end
|
|
|
// AND - Logical AND
|
// AND - Logical AND
|
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
|
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
|
result = A & alu_a;
|
//result = A & alu_a;
|
|
result = alu_result & alu_a;
|
end
|
end
|
|
|
// CMP - Compare
|
// CMP - Compare
|
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
|
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
|
result = A - alu_a;
|
//result = A - alu_a;
|
STATUS[C] = (A >= alu_a) ? 1 : 0;
|
result = alu_result - alu_a;
|
|
//STATUS[C] = (A >= alu_a) ? 1 : 0;
|
|
STATUS[C] = (alu_result >= alu_a) ? 1 : 0;
|
end
|
end
|
|
|
// EOR - Exclusive OR
|
// EOR - Exclusive OR
|
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
|
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
|
result = A ^ alu_a;
|
result = alu_result ^ alu_a;
|
|
//result = A ^ alu_a;
|
//$display("op1 ^ op2 = result");
|
//$display("op1 ^ op2 = result");
|
//$display("%d ^ %d = %d", op1, op2, result);
|
//$display("%d ^ %d = %d", op1, op2, result);
|
end
|
end
|
|
|
// LDA - Load Accumulator
|
// LDA - Load Accumulator
|
| Line 410... |
Line 424... |
result = alu_a;
|
result = alu_a;
|
end
|
end
|
|
|
// ORA - Logical OR
|
// ORA - Logical OR
|
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
|
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
|
result = A | alu_a;
|
//result = A | alu_a;
|
|
result = alu_result | alu_a;
|
end
|
end
|
|
|
// SBC - Subtract with Carry
|
// SBC - Subtract with Carry
|
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
|
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
|
if (alu_status[D] == 1) begin
|
|
op2 = ~op2;
|
op2 = ~op2;
|
AL = A[3:0] + alu_a[3:0] + alu_status[C];
|
if (alu_status[D] == 1) begin
|
AH = A[7:4] + alu_a[7:4];
|
//AL = A[3:0] + alu_a[3:0] + alu_status[C];
|
|
AL = op1[3:0] + op2[3:0] + alu_status[C];
|
|
//AH = A[7:4] + alu_a[7:4];
|
|
AH = op1[7:4] + op2[7:4];
|
if (AL > 9) begin
|
if (AL > 9) begin
|
bcdh = AH + (AL / 10);
|
bcdh = AH + (AL / 10);
|
bcdl = AL % 10;
|
bcdl = AL % 10;
|
end
|
end
|
else begin
|
else begin
|
| Line 439... |
Line 456... |
end
|
end
|
result = {bcdh2[3:0],bcdl[3:0]};
|
result = {bcdh2[3:0],bcdl[3:0]};
|
end
|
end
|
else begin
|
else begin
|
//$display("MODO NORMAL");
|
//$display("MODO NORMAL");
|
{STATUS[C],result} = op1 + op2 + alu_status[C];
|
result = op1 + op2 + alu_status[C];
|
|
STATUS[C] = ~result[7];
|
end
|
end
|
/* if (alu_status[D] == 1) begin
|
/* if (alu_status[D] == 1) begin
|
bcdl = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
|
bcdl = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
|
bcdh = op1[7:4] - op2[7:4];
|
bcdh = op1[7:4] - op2[7:4];
|
if (bcdl > 9) begin
|
if (bcdl > 9) begin
|
| Line 471... |
Line 489... |
end
|
end
|
|
|
// ASL - Arithmetic Shift Left
|
// ASL - Arithmetic Shift Left
|
ASL_ACC : begin
|
ASL_ACC : begin
|
//{STATUS[C],result} = A << 1;
|
//{STATUS[C],result} = A << 1;
|
{STATUS[C],result} = {A,1'b0};
|
//{STATUS[C],result} = {A,1'b0};
|
|
{STATUS[C],result} = {alu_result,1'b0};
|
end
|
end
|
ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
|
ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
|
//{STATUS[C],result} = alu_a << 1;
|
//{STATUS[C],result} = alu_a << 1;
|
{STATUS[C],result} = {alu_a,1'b0};
|
{STATUS[C],result} = {alu_a,1'b0};
|
end
|
end
|
|
|
// LSR - Logical Shift Right
|
// LSR - Logical Shift Right
|
LSR_ACC: begin
|
LSR_ACC: begin
|
//{result, STATUS[C]} = A >> 1;
|
//{result, STATUS[C]} = A >> 1;
|
{result,STATUS[C]} = {1'b0,A};
|
//{result,STATUS[C]} = {1'b0,A};
|
|
{result,STATUS[C]} = {1'b0,alu_result};
|
end
|
end
|
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
|
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
|
//{result, STATUS[C]} = alu_a >> 1;
|
//{result, STATUS[C]} = alu_a >> 1;
|
{result,STATUS[C]} = {1'b0,alu_a};
|
{result,STATUS[C]} = {1'b0,alu_a};
|
end
|
end
|
|
|
// ROL - Rotate Left
|
// ROL - Rotate Left
|
ROL_ACC : begin
|
ROL_ACC : begin
|
{STATUS[C],result} = {A,alu_status[C]};
|
//{STATUS[C],result} = {A,alu_status[C]};
|
|
{STATUS[C],result} = {alu_result,alu_status[C]};
|
end
|
end
|
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
|
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
|
{STATUS[C],result} = {alu_a,alu_status[C]};
|
{STATUS[C],result} = {alu_a,alu_status[C]};
|
end
|
end
|
|
|
// ROR - Rotate Right
|
// ROR - Rotate Right
|
ROR_ACC : begin
|
ROR_ACC : begin
|
{result,STATUS[C]} = {alu_status[C],A};
|
//{result,STATUS[C]} = {alu_status[C],A};
|
|
{result,STATUS[C]} = {alu_status[C],alu_result};
|
end
|
end
|
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
|
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
|
{result, STATUS[C]} = {alu_status[C], alu_a};
|
{result, STATUS[C]} = {alu_status[C], alu_a};
|
end
|
end
|
|
|
// CPX - Compare X Register
|
// CPX - Compare X Register
|
CPX_IMM, CPX_ZPG, CPX_ABS : begin
|
CPX_IMM, CPX_ZPG, CPX_ABS : begin
|
result = X - alu_a;
|
//result = X - alu_a;
|
STATUS[C] = (X >= alu_a) ? 1 : 0;
|
result = alu_x - alu_a;
|
|
//STATUS[C] = (X >= alu_a) ? 1 : 0;
|
|
STATUS[C] = (alu_x >= alu_a) ? 1 : 0;
|
end
|
end
|
|
|
// CPY - Compare Y Register
|
// CPY - Compare Y Register
|
CPY_IMM, CPY_ZPG, CPY_ABS : begin
|
CPY_IMM, CPY_ZPG, CPY_ABS : begin
|
result = Y - alu_a;
|
//result = Y - alu_a;
|
STATUS[C] = (Y >= alu_a) ? 1 : 0;
|
result = alu_y - alu_a;
|
|
//STATUS[C] = (Y >= alu_a) ? 1 : 0;
|
|
STATUS[C] = (alu_y >= alu_a) ? 1 : 0;
|
end
|
end
|
|
|
default: begin // NON-DEFAULT OPCODES FALL HERE
|
default: begin // NON-DEFAULT OPCODES FALL HERE
|
end
|
end
|
endcase
|
endcase
|
