| Line 69... |
Line 69... |
reg [7:0] bcdl;
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reg [7:0] bcdl;
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reg [7:0] bcdh;
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reg [7:0] bcdh;
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reg [7:0] bcdh2;
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reg [7:0] bcdh2;
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reg [7:0] AL;
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reg [7:0] AL;
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reg [7:0] AH;
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reg [7:0] AH;
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//reg C_aux;
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reg C_aux;
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reg sign;
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reg sign;
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`include "t6507lp_package.v"
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`include "t6507lp_package.v"
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or negedge reset_n)
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| Line 87... |
Line 87... |
alu_status[Z] <= 1;
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alu_status[Z] <= 1;
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alu_status[I] <= 0;
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alu_status[I] <= 0;
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alu_status[B] <= 0;
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alu_status[B] <= 0;
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alu_status[D] <= 0;
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alu_status[D] <= 0;
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A <= 0;
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A <= 0;
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//X <= 0;
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//Y <= 0;
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alu_x <= 0;
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alu_x <= 0;
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alu_y <= 0;
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alu_y <= 0;
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end
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end
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else if ( alu_enable == 1 ) begin
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else if ( alu_enable == 1 ) begin
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case (alu_opcode)
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case (alu_opcode)
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| Line 108... |
Line 106... |
alu_result <= result;
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alu_result <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
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LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
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begin
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begin
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//X <= result;
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alu_x <= result;
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alu_x <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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TXS_IMP :
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TXS_IMP :
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begin
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begin
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//X <= result;
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alu_x <= result;
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alu_x <= result;
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end
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end
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TXA_IMP, TYA_IMP :
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TXA_IMP, TYA_IMP :
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begin
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begin
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A <= result;
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A <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
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LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
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begin
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begin
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//Y <= result;
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alu_y <= result;
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alu_y <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
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CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
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CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :
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CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :
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| Line 198... |
Line 193... |
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
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ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
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begin
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begin
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alu_result <= result;
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alu_result <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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//PHP_IMP : begin
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//end
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default : begin
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default : begin
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//$display("ERROR");
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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always @ (*) begin
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always @ (*) begin
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if (alu_enable == 1) begin
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if (alu_enable == 1) begin
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//op1 = A;
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op1 = A;
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op1 = A;
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op2 = alu_a;
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op2 = alu_a;
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result = alu_result;
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result = alu_result;
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STATUS[N] = alu_status[N];
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STATUS[N] = alu_status[N];
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STATUS[C] = alu_status[C];
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STATUS[C] = alu_status[C];
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| Line 232... |
Line 223... |
sign = op2[7];
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sign = op2[7];
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case (alu_opcode)
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case (alu_opcode)
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// BIT - Bit Test
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// BIT - Bit Test
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BIT_ZPG, BIT_ABS: begin
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BIT_ZPG, BIT_ABS: begin
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//result = A & alu_a;
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result = A & alu_a;
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result = A & alu_a;
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end
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end
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// BRK - Force Interrupt
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// BRK - Force Interrupt
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//BRK_IMP: begin
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//BRK_IMP: begin
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| Line 281... |
Line 271... |
// STA - Store Accumulator
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// STA - Store Accumulator
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// PHA - Push A
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// PHA - Push A
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// TAX - Transfer Accumulator to X
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// TAX - Transfer Accumulator to X
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// TAY - Transfer Accumulator to Y
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// TAY - Transfer Accumulator to Y
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TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
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TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
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//result = A;
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result = A;
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result = A;
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end
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end
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// STX - Store X Register
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// STX - Store X Register
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// TXA - Transfer X to Accumulator
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// TXA - Transfer X to Accumulator
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// TXS - Transfer X to Stack pointer
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// TXS - Transfer X to Stack pointer
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STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
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STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
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//result = X;
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result = alu_x;
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result = alu_x;
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end
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end
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// STY - Store Y Register
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// STY - Store Y Register
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// TYA - Transfer Y to Accumulator
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// TYA - Transfer Y to Accumulator
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STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
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STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
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//result = Y;
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result = alu_y;
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result = alu_y;
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end
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end
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// SEC - Set Carry Flag
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// SEC - Set Carry Flag
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//SEC_IMP: begin
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//SEC_IMP: begin
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| Line 322... |
Line 309... |
result = alu_a + 1;
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result = alu_a + 1;
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end
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end
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// INX - Increment X Register
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// INX - Increment X Register
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INX_IMP: begin
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INX_IMP: begin
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//result = X + 1;
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result = alu_x + 1;
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result = alu_x + 1;
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end
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end
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// INY - Increment Y Register
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// INY - Increment Y Register
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INY_IMP : begin
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INY_IMP : begin
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//result = Y + 1;
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result = alu_y + 1;
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result = alu_y + 1;
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end
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end
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// DEC - Decrement memory
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// DEC - Decrement memory
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DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
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DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
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result = alu_a - 1;
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result = alu_a - 1;
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end
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end
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// DEX - Decrement X register
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// DEX - Decrement X register
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DEX_IMP: begin
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DEX_IMP: begin
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//result = X - 1;
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result = alu_x - 1;
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result = alu_x - 1;
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end
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end
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// DEY - Decrement Y Register
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// DEY - Decrement Y Register
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DEY_IMP: begin
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DEY_IMP: begin
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//result = Y - 1;
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result = alu_y - 1;
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result = alu_y - 1;
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end
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end
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// ADC - Add with carry
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// ADC - Add with carry
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// TODO: verify synthesis for % operand
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// TODO: verify synthesis for % operand
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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if (alu_status[D] == 1) begin
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if (alu_status[D] == 1) begin
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//$display("MODO DECIMAL");
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//$display("MODO DECIMAL");
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//AL = A[3:0] + alu_a[3:0] + alu_status[C];
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//AL = A[3:0] + alu_a[3:0] + alu_status[C];
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AL = op1[3:0] + op2[3:0] + alu_status[C];
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AL = op1[3:0] + op2[3:0] + alu_status[C];
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//$display("op1[3:0] + op2[3:0] + alu_status[C]",op1[3:0], op2[3:0], alu_status[C]);
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//AH = A[7:4] + alu_a[7:4];
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//AH = A[7:4] + alu_a[7:4];
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AH = op1[7:4] + op2[7:4];
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AH = op1[7:4] + op2[7:4] + AL[4];
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$display("AL = %d", AL);
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//$display("op1[7:4] + op2[7:4] + AL[4]",op1[7:4], op2[7:4], AL[4]);
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$display("AH = %d", AH);
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if (AL > 9) bcdl = AL + 6;
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if (AL > 9) begin
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else bcdl = AL;
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bcdh = AH + (AL / 10);
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STATUS[Z] =
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bcdl = AL % 10;
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if (bcdh > 9)
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end
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bcdh2 = bcdh + 6;
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else begin
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else bcdh2 = bcdh;
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bcdh = AH;
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bcdl = AL;
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end
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// ok
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if (bcdh > 9) begin
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STATUS[C] = 1;
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bcdh2 = bcdh % 10;
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end
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else begin
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STATUS[C] = 0;
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bcdh2 = bcdh;
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end
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//$display("bcdh2 = %d", bcdh2);
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//$display("bcdh2 = %d", bcdh2);
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//$display("bcdl = %d", bcdl);
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//$display("bcdl = %d", bcdl);
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STATUS[C] = AH[4];
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result = {bcdh2[3:0],bcdl[3:0]};
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result = {bcdh2[3:0],bcdl[3:0]};
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end
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end
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else begin
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else begin
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//$display("MODO NORMAL");
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//$display("MODO NORMAL");
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{STATUS[C],result} = op1 + op2 + alu_status[C];
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{STATUS[C],result} = op1 + op2 + alu_status[C];
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| Line 396... |
Line 367... |
STATUS[V] = 0;
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STATUS[V] = 0;
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end
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end
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// AND - Logical AND
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// AND - Logical AND
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
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//result = A & alu_a;
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result = A & alu_a;
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result = A & alu_a;
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end
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end
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// CMP - Compare
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// CMP - Compare
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CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
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CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
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//result = A - alu_a;
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result = A - alu_a;
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result = A - alu_a;
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//STATUS[C] = (A >= alu_a) ? 1 : 0;
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STATUS[C] = (A >= alu_a) ? 1 : 0;
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STATUS[C] = (A >= alu_a) ? 1 : 0;
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end
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end
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// EOR - Exclusive OR
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// EOR - Exclusive OR
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EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
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EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
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result = A ^ alu_a;
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result = A ^ alu_a;
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//result = A ^ alu_a;
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//$display("op1 ^ op2 = result");
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//$display("%d ^ %d = %d", op1, op2, result);
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end
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end
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// LDA - Load Accumulator
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// LDA - Load Accumulator
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// LDX - Load X Register
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// LDX - Load X Register
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// LDY - Load Y Register
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// LDY - Load Y Register
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