| Line 42... |
Line 42... |
//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module t6507lp_alu(
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module t6507lp_alu(clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y);
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clk,
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reset_n,
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`include "t6507lp_package.v"
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alu_enable,
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alu_result,
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localparam DATA_SIZE = 8;
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alu_status,
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localparam [3:0] BCD_HIGH_LIMIT = 4'd9;
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alu_opcode,
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localparam [3:0] BCD_FIX = 8'd6;
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alu_a,
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alu_x,
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alu_y
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);
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input wire clk;
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input wire clk;
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input wire reset_n;
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input wire reset_n;
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input wire alu_enable;
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input wire alu_enable;
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input wire [7:0] alu_opcode;
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input wire [DATA_SIZE - 1:0] alu_opcode;
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input wire [7:0] alu_a;
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input wire [DATA_SIZE - 1:0] alu_a;
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output reg [7:0] alu_result;
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output reg [DATA_SIZE - 1:0] alu_result;
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output reg [7:0] alu_status;
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output reg [DATA_SIZE - 1:0] alu_status;
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output reg [7:0] alu_x;
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output reg [DATA_SIZE - 1:0] alu_x;
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output reg [7:0] alu_y;
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output reg [DATA_SIZE - 1:0] alu_y;
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reg [7:0] A;
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reg [DATA_SIZE - 1:0] A;
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reg [7:0] STATUS;
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reg [DATA_SIZE - 1:0] STATUS;
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reg [9:0] result;
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reg [DATA_SIZE + 1:0] result;
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reg [7:0] op1;
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reg [DATA_SIZE - 1:0] op1;
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reg [7:0] op2;
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reg [DATA_SIZE - 1:0] op2;
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reg [7:0] bcdl;
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reg [DATA_SIZE - 1:0] bcdl;
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reg [7:0] bcdh;
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reg [DATA_SIZE - 1:0] bcdh;
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reg [7:0] bcdh2;
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reg [DATA_SIZE - 1:0] bcdh2;
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reg [7:0] AL;
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reg [DATA_SIZE - 1:0] AL;
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reg [7:0] AH;
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reg [DATA_SIZE - 1:0] AH;
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reg C_aux;
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reg sign;
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`include "t6507lp_package.v"
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or negedge reset_n)
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begin
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begin
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if (reset_n == 0) begin
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if (reset_n == 1'b0) begin
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alu_result <= 0;
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alu_result <= 10'd0;
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alu_status[C] <= 0;
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alu_status[C] <= 1'b0;
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alu_status[N] <= 0;
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alu_status[N] <= 1'b0;
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alu_status[V] <= 0;
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alu_status[V] <= 1'b0;
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alu_status[5] <= 1;
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alu_status[5] <= 1'b1;
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alu_status[Z] <= 1;
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alu_status[Z] <= 1'b1;
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alu_status[I] <= 0;
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alu_status[I] <= 1'b0;
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alu_status[B] <= 0;
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alu_status[B] <= 1'b0;
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alu_status[D] <= 0;
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alu_status[D] <= 1'b0;
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A <= 0;
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A <= 8'd0;
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alu_x <= 0;
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alu_x <= 8'd0;
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alu_y <= 0;
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alu_y <= 8'd0;
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end
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end
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else if ( alu_enable == 1 ) begin
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else if ( alu_enable == 1'b1 ) begin
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case (alu_opcode)
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case (alu_opcode)
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY,
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY,
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ADC_IDX, ADC_IDY, AND_IMM, AND_ZPG, AND_ZPX, AND_ABS,
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ADC_IDX, ADC_IDY, AND_IMM, AND_ZPG, AND_ZPX, AND_ABS,
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AND_ABX, AND_ABY, AND_IDX, AND_IDY, ASL_ACC, EOR_IMM,
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AND_ABX, AND_ABY, AND_IDX, AND_IDY, ASL_ACC, EOR_IMM,
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EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
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EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
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| Line 143... |
Line 135... |
end
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end
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STY_ZPG, STY_ZPX, STY_ABS : begin
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STY_ZPG, STY_ZPX, STY_ABS : begin
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alu_y <= result[7:0];
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alu_y <= result[7:0];
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end
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end
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SEC_IMP : begin
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SEC_IMP : begin
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alu_status[C] <= 1;
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alu_status[C] <= 1'b1;
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end
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end
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SED_IMP : begin
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SED_IMP : begin
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alu_status[D] <= 1;
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alu_status[D] <= 1'b1;
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end
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end
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SEI_IMP : begin
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SEI_IMP : begin
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alu_status[I] <= 1;
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alu_status[I] <= 1'b1;
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end
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end
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CLC_IMP : begin
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CLC_IMP : begin
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alu_status[C] <= 0;
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alu_status[C] <= 1'b0;
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end
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end
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CLD_IMP : begin
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CLD_IMP : begin
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alu_status[D] <= 0;
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alu_status[D] <= 1'b0;
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end
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end
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CLI_IMP : begin
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CLI_IMP : begin
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alu_status[I] <= 0;
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alu_status[I] <= 1'b0;
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end
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end
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CLV_IMP : begin
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CLV_IMP : begin
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alu_status[V] <= 0;
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alu_status[V] <= 1'b0;
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end
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end
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BRK_IMP : begin
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BRK_IMP : begin
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alu_status[B] <= 1;
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alu_status[B] <= 1'b1;
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end
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end
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PLP_IMP, RTI_IMP : begin
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PLP_IMP, RTI_IMP : begin
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alu_status[C] <= alu_a[C];
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alu_status[C] <= alu_a[C];
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alu_status[Z] <= alu_a[Z];
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alu_status[Z] <= alu_a[Z];
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alu_status[I] <= alu_a[I];
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alu_status[I] <= alu_a[I];
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alu_status[D] <= alu_a[D];
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alu_status[D] <= alu_a[D];
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alu_status[B] <= alu_a[B];
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alu_status[B] <= alu_a[B];
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alu_status[V] <= alu_a[V];
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alu_status[V] <= alu_a[V];
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alu_status[N] <= alu_a[N];
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alu_status[N] <= alu_a[N];
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alu_status[5] <= 1;
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alu_status[5] <= 1'b1;
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end
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end
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BIT_ZPG, BIT_ABS : begin
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BIT_ZPG, BIT_ABS : begin
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alu_status[Z] <= STATUS[Z];
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alu_status[Z] <= STATUS[Z];
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alu_status[V] <= alu_a[6];
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alu_status[V] <= alu_a[6];
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alu_status[N] <= alu_a[7];
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alu_status[N] <= alu_a[7];
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Line 182... |
begin
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begin
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alu_result <= result[7:0];
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alu_result <= result[7:0];
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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default : begin
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default : begin
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alu_result <= 8'hFF;
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alu_status <= 8'hFF;
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A <= 8'hFF;
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alu_x <= 8'hFF;
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alu_y <= 8'hFF;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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always @ (*) begin
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always @ (*) begin
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if (alu_enable == 1) begin
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op1 = A;
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op1 = A;
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op2 = alu_a;
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op2 = alu_a;
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result = A[7:0];
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result = {2'd0, A[7:0]};
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result[9:8] = 0;
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result[9:8] = 2'b00;
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STATUS[N] = alu_status[N];
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STATUS[N] = alu_status[N];
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STATUS[C] = alu_status[C];
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STATUS[C] = alu_status[C];
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STATUS[V] = alu_status[V];
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STATUS[V] = alu_status[V];
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STATUS[B] = alu_status[B];
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STATUS[B] = alu_status[B];
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STATUS[I] = alu_status[I];
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STATUS[I] = alu_status[I];
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STATUS[D] = alu_status[D];
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STATUS[D] = alu_status[D];
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STATUS[Z] = alu_status[Z];
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STATUS[Z] = alu_status[Z];
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STATUS[5] = 1;
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STATUS[5] = 1'b1;
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bcdl = 0;
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bcdl = 8'd0;
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bcdh = 0;
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bcdh = 8'd0;
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bcdh2 = 0;
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bcdh2 = 8'd0;
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AL = 0;
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AL = 8'd0;
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AH = 0;
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AH = 8'd0;
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sign = op2[7];
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if (alu_enable == 1'b1) begin
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case (alu_opcode)
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case (alu_opcode)
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// BIT - Bit Test
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// BIT - Bit Test
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BIT_ZPG, BIT_ABS: begin
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BIT_ZPG, BIT_ABS: begin
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result[7:0] = A & alu_a;
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result[7:0] = A & alu_a;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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// PLA - Pull Accumulator
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// PLA - Pull Accumulator
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PLA_IMP : begin
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PLA_IMP : begin
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result[7:0] = alu_a;
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result[7:0] = alu_a;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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// TAX - Transfer Accumulator to X
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// TAX - Transfer Accumulator to X
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// TAY - Transfer Accumulator to Y
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// TAY - Transfer Accumulator to Y
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// PHA - Push Accumulator
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// PHA - Push Accumulator
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// STA - Store Accumulator
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// STA - Store Accumulator
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TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX,
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TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX,
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STA_ABY, STA_IDX, STA_IDY : begin
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STA_ABY, STA_IDX, STA_IDY : begin
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result[7:0] = A;
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result[7:0] = A;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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// STX - Store X Register
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// STX - Store X Register
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// TXA - Transfer X to Accumulator
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// TXA - Transfer X to Accumulator
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// TXS - Transfer X to Stack pointer
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// TXS - Transfer X to Stack pointer
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STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
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STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
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result[7:0] = alu_x;
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result[7:0] = alu_x;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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// STY - Store Y Register
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// STY - Store Y Register
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// TYA - Transfer Y to Accumulator
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// TYA - Transfer Y to Accumulator
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STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
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STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
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result[7:0] = alu_y;
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result[7:0] = alu_y;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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// INC - Increment memory
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// INC - Increment memory
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INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
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INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
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result[7:0] = alu_a + 1;
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result[7:0] = alu_a + 8'd1;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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// INX - Increment X Register
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// INX - Increment X Register
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INX_IMP: begin
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INX_IMP: begin
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result[7:0] = alu_x + 1;
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result[7:0] = alu_x + 8'd1;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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// INY - Increment Y Register
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// INY - Increment Y Register
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INY_IMP : begin
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INY_IMP : begin
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result[7:0] = alu_y + 1;
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result[7:0] = alu_y + 8'd1;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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// DEC - Decrement memory
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// DEC - Decrement memory
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DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
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DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
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result[7:0] = alu_a - 1;
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result[7:0] = alu_a - 8'd1;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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// DEX - Decrement X register
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// DEX - Decrement X register
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DEX_IMP: begin
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DEX_IMP: begin
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result[7:0] = alu_x - 1;
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result[7:0] = alu_x - 8'd1;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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// DEY - Decrement Y Register
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// DEY - Decrement Y Register
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DEY_IMP: begin
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DEY_IMP: begin
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result[7:0] = alu_y - 1;
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result[7:0] = alu_y - 8'd1;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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// ADC - Add with carry
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// ADC - Add with carry
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS,
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS,
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ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
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if (!alu_status[D]) begin
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if (!alu_status[D]) begin
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result = op1 + op2 + alu_status[C];
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result = op1 + op2 + {7'd0, alu_status[C]}; // this looks so ugly but the operands are all 8 bits now
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != result[7])) ? 1 : 0;
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STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != result[7])) ? 1'b1 : 1'b0;
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STATUS[C] = result[8];
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STATUS[C] = result[8];
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end
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end
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else begin
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else begin
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AL = op1[3:0] + op2[3:0] + alu_status[C];
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AL = op1[3:0] + op2[3:0] + {7'd0, alu_status[C]};
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AH = op1[7:4] + op2[7:4];
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AH = op1[7:4] + op2[7:4];
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STATUS[Z] = (AL == 0 && AH == 0) ? 1 : 0;
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STATUS[Z] = (AL == 0 && AH == 0) ? 1'b1 : 1'b0;
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if (AL > 9) begin
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if (AL > {4'd0,BCD_HIGH_LIMIT}) begin
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bcdl = AL + 6;
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bcdl = AL + {4'd0, BCD_FIX};
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bcdh = AH + 1;
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bcdh = AH + 8'd1;
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end
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end
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else begin
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else begin
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bcdl = AL;
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bcdl = AL;
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bcdh = AH;
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bcdh = AH;
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end
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end
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STATUS[N] = bcdh[3];
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STATUS[N] = bcdh[3];
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STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != bcdh[3])) ? 1 : 0;
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STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != bcdh[3])) ? 1'b1 : 1'b0;
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if (bcdh > 9) begin
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if (bcdh > {4'd0, BCD_HIGH_LIMIT}) begin
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bcdh2 = bcdh + 6;
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bcdh2 = bcdh + {4'd0, BCD_FIX};
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end
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end
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else begin
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else begin
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bcdh2 = bcdh;
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bcdh2 = bcdh;
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end
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end
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STATUS[C] = bcdh2[4] || bcdh2[5];
|
STATUS[C] = bcdh2[4] || bcdh2[5];
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| Line 341... |
Line 337... |
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// AND - Logical AND
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// AND - Logical AND
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX,
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX,
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AND_IDY : begin
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AND_IDY : begin
|
result[7:0] = A & alu_a;
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result[7:0] = A & alu_a;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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|
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// CMP - Compare
|
// CMP - Compare
|
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX,
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CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX,
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CMP_IDY : begin
|
CMP_IDY : begin
|
result[7:0] = A - alu_a;
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result[7:0] = A - alu_a;
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STATUS[C] = (A >= alu_a) ? 1 : 0;
|
STATUS[C] = (A >= alu_a) ? 1'b1 : 1'b0;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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|
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// EOR - Exclusive OR
|
// EOR - Exclusive OR
|
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY,
|
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY,
|
EOR_IDX, EOR_IDY : begin
|
EOR_IDX, EOR_IDY : begin
|
result[7:0] = A ^ alu_a;
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result[7:0] = A ^ alu_a;
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STATUS[Z] = (result == 0) ? 1 : 0;
|
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
|
STATUS[N] = result[7];
|
STATUS[N] = result[7];
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end
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end
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|
|
// LDA - Load Accumulator
|
// LDA - Load Accumulator
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// LDX - Load X Register
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// LDX - Load X Register
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| Line 370... |
Line 366... |
// TSX - Transfer Stack Pointer to X
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// TSX - Transfer Stack Pointer to X
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LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX,
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LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX,
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LDA_IDY, LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, LDY_IMM,
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LDA_IDY, LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, LDY_IMM,
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LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TSX_IMP : begin
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LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TSX_IMP : begin
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result[7:0] = alu_a;
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result[7:0] = alu_a;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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|
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// ORA - Logical OR
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// ORA - Logical OR
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ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX,
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ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX,
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ORA_IDY : begin
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ORA_IDY : begin
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result[7:0] = A | alu_a;
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result[7:0] = A | alu_a;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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|
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// SBC - Subtract with Carry
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// SBC - Subtract with Carry
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SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX,
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SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX,
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SBC_IDY : begin
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SBC_IDY : begin
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result = op1 - op2 - (1 - alu_status[C]);
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result = op1 - op2 - (1'b1 - alu_status[C]);
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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STATUS[V] = ((op1[7] ^ op2[7]) && (op1[7] ^ result[7])) ? 1 : 0;
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STATUS[V] = ((op1[7] ^ op2[7]) && (op1[7] ^ result[7])) ? 1'b1 : 1'b0;
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[C] = ~(result[8] || result[9]);
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STATUS[C] = ~(result[8] || result[9]);
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if (alu_status[D]) begin
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if (alu_status[D]) begin
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AL = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
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AL = op1[3:0] - op2[3:0] - (1'b1 - alu_status[C]);
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AH = op1[7:4] - op2[7:4];
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AH = op1[7:4] - op2[7:4];
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if (AL[4]) begin
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if (AL[4]) begin
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bcdl = AL - 6;
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bcdl = AL - {4'd0, BCD_FIX};
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bcdh = AH - 1;
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bcdh = AH - 8'd1;
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end
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end
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else begin
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else begin
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bcdl = AL;
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bcdl = AL;
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bcdh = AH;
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bcdh = AH;
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end
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end
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if (bcdh[4]) begin
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if (bcdh[4]) begin
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bcdh2 = bcdh - 6;
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bcdh2 = bcdh - {4'd0, BCD_FIX};
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end
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end
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else begin
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else begin
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bcdh2 = bcdh;
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bcdh2 = bcdh;
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end
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end
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result[7:0] = {bcdh2[3:0],bcdl[3:0]};
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result[7:0] = {bcdh2[3:0],bcdl[3:0]};
|
| Line 414... |
Line 410... |
end
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end
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|
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// ASL - Arithmetic Shift Left
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// ASL - Arithmetic Shift Left
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ASL_ACC : begin
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ASL_ACC : begin
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{STATUS[C],result[7:0]} = {A,1'b0};
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{STATUS[C],result[7:0]} = {A,1'b0};
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
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ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
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{STATUS[C],result[7:0]} = {alu_a,1'b0};
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{STATUS[C],result[7:0]} = {alu_a,1'b0};
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STATUS[Z] = (result == 0) ? 1 : 0;
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STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
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STATUS[N] = result[7];
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STATUS[N] = result[7];
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end
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end
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|
|
// LSR - Logical Shift Right
|
// LSR - Logical Shift Right
|
LSR_ACC: begin
|
LSR_ACC: begin
|
{result[7:0],STATUS[C]} = {1'b0,A};
|
{result[7:0],STATUS[C]} = {1'b0,A};
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STATUS[Z] = (result == 0) ? 1 : 0;
|
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
|
STATUS[N] = result[7];
|
STATUS[N] = result[7];
|
end
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end
|
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
|
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
|
{result[7:0],STATUS[C]} = {1'b0,alu_a};
|
{result[7:0],STATUS[C]} = {1'b0,alu_a};
|
STATUS[Z] = (result == 0) ? 1 : 0;
|
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
|
STATUS[N] = result[7];
|
STATUS[N] = result[7];
|
end
|
end
|
|
|
// ROL - Rotate Left
|
// ROL - Rotate Left
|
ROL_ACC : begin
|
ROL_ACC : begin
|
{STATUS[C],result[7:0]} = {A,alu_status[C]};
|
{STATUS[C],result[7:0]} = {A,alu_status[C]};
|
STATUS[Z] = (result == 0) ? 1 : 0;
|
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
|
STATUS[N] = result[7];
|
STATUS[N] = result[7];
|
end
|
end
|
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
|
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
|
{STATUS[C],result[7:0]} = {alu_a,alu_status[C]};
|
{STATUS[C],result[7:0]} = {alu_a,alu_status[C]};
|
STATUS[Z] = (result == 0) ? 1 : 0;
|
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
|
STATUS[N] = result[7];
|
STATUS[N] = result[7];
|
end
|
end
|
|
|
// ROR - Rotate Right
|
// ROR - Rotate Right
|
ROR_ACC : begin
|
ROR_ACC : begin
|
{result[7:0],STATUS[C]} = {alu_status[C],A};
|
{result[7:0],STATUS[C]} = {alu_status[C],A};
|
STATUS[Z] = (result == 0) ? 1 : 0;
|
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
|
STATUS[N] = result[7];
|
STATUS[N] = result[7];
|
end
|
end
|
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
|
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
|
{result[7:0], STATUS[C]} = {alu_status[C], alu_a};
|
{result[7:0], STATUS[C]} = {alu_status[C], alu_a};
|
STATUS[Z] = (result == 0) ? 1 : 0;
|
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
|
STATUS[N] = result[7];
|
STATUS[N] = result[7];
|
end
|
end
|
|
|
// CPX - Compare X Register
|
// CPX - Compare X Register
|
CPX_IMM, CPX_ZPG, CPX_ABS : begin
|
CPX_IMM, CPX_ZPG, CPX_ABS : begin
|
result[7:0] = alu_x - alu_a;
|
result[7:0] = alu_x - alu_a;
|
STATUS[C] = (alu_x >= alu_a) ? 1 : 0;
|
STATUS[C] = (alu_x >= alu_a) ? 1'b1 : 1'b0;
|
STATUS[Z] = (result == 0) ? 1 : 0;
|
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
|
STATUS[N] = result[7];
|
STATUS[N] = result[7];
|
end
|
end
|
|
|
// CPY - Compare Y Register
|
// CPY - Compare Y Register
|
CPY_IMM, CPY_ZPG, CPY_ABS : begin
|
CPY_IMM, CPY_ZPG, CPY_ABS : begin
|
result[7:0] = alu_y - alu_a;
|
result[7:0] = alu_y - alu_a;
|
STATUS[C] = (alu_y >= alu_a) ? 1 : 0;
|
STATUS[C] = (alu_y >= alu_a) ? 1'b1 : 1'b0;
|
STATUS[Z] = (result == 0) ? 1 : 0;
|
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
|
STATUS[N] = result[7];
|
STATUS[N] = result[7];
|
end
|
end
|
|
|
default: begin
|
default: begin
|
|
result = 10'h3FF;
|
|
STATUS = 8'hFF;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
endmodule
|
endmodule
|
