OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_tb.v] - Diff between revs 148 and 149

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 148 Rev 149
Line 89... Line 89...
        // ADC
        // ADC
        alu_opcode = ADC_IMM;
        alu_opcode = ADC_IMM;
        alu_a = 1;
        alu_a = 1;
        for (i = 0; i < 1000; i = i + 1)
        for (i = 0; i < 1000; i = i + 1)
        begin
        begin
 
                alu_a = $random;
                @(negedge clk);
                @(negedge clk);
                $display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
                //$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
                $display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
                //$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
                $display("op1 = %d op2 = %d  c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], DUT.result);
                //$display("op1 = %d op2 = %d  c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], DUT.result);
                {alu_status_expected[C], alu_result_expected} = alu_a + alu_result_expected + alu_status_expected[C];
                {alu_status_expected[C], alu_result_expected} = alu_a + alu_result_expected + alu_status_expected[C];
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                alu_status_expected[N] = alu_result_expected[7];
                alu_status_expected[V] = ((alu_a[7] == DUT.A[7]) && (alu_a[7] != alu_result_expected[7]));
                alu_status_expected[V] = ((alu_a[7] == DUT.A[7]) && (alu_a[7] != alu_result_expected[7]));
                check();
                check();
Line 424... Line 425...
        alu_opcode = BIT_ZPG;
        alu_opcode = BIT_ZPG;
        for (i = 0; i < 1000; i = i + 1)
        for (i = 0; i < 1000; i = i + 1)
        begin
        begin
                alu_a = i;
                alu_a = i;
                @(negedge clk);
                @(negedge clk);
                $display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
                //$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
                $display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
                //$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
                $display("op1 = %d op2 = %d  c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
                //$display("op1 = %d op2 = %d  c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
                alu_status_expected[Z] = ((alu_a & alu_result_expected) == 0) ? 1 : 0;
                alu_status_expected[Z] = ((alu_a & alu_result_expected) == 0) ? 1 : 0;
                alu_status_expected[V] = alu_a[6];
                alu_status_expected[V] = alu_a[6];
                alu_status_expected[N] = alu_a[7];
                alu_status_expected[N] = alu_a[7];
                check();
                check();
        end
        end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.