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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_tb.v] - Diff between revs 149 and 150

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Rev 149 Rev 150
Line 42... Line 42...
                $display("               RESULTS       EXPECTED");
                $display("               RESULTS       EXPECTED");
                $display("alu_result       %h             %h   ", alu_result, alu_result_expected);
                $display("alu_result       %h             %h   ", alu_result, alu_result_expected);
                $display("alu_status    %b       %b   ", alu_status, alu_status_expected);
                $display("alu_status    %b       %b   ", alu_status, alu_status_expected);
                $display("alu_x            %h             %h   ", alu_x,      alu_x_expected     );
                $display("alu_x            %h             %h   ", alu_x,      alu_x_expected     );
                $display("alu_y            %h             %h   ", alu_y,      alu_y_expected     );
                $display("alu_y            %h             %h   ", alu_y,      alu_y_expected     );
                if ((alu_result_expected != alu_result) || (alu_status_expected != alu_status) || (alu_x_expected != alu_x) || (alu_y_expected != alu_y))
                if ((alu_result_expected == alu_result) && (alu_status_expected == alu_status) && (alu_x_expected == alu_x) && (alu_y_expected == alu_y))
                begin
                begin
                        $display("ERROR at instruction %h",alu_opcode);
                        $display("Instruction %h... OK!", alu_opcode);
                        $finish;
 
                end
                end
                else
                else
                begin
                begin
                        $display("Instruction %h... OK!", alu_opcode);
                        $display("ERROR at instruction %h",alu_opcode);
 
                        $finish;
                end
                end
        end
        end
endtask
endtask
 
 
 
 
Line 65... Line 65...
begin
begin
        // Reset
        // Reset
        clk = 0;
        clk = 0;
        reset_n = 0;
        reset_n = 0;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        //@(negedge clk);
        reset_n = 1;
        reset_n = 1;
        alu_enable = 1;
        alu_enable = 1;
        alu_result_expected = 8'h00;
        alu_result_expected = 8'h00;
        alu_status_expected = 8'b00100010;
        alu_status_expected = 8'b00100010;
        alu_x_expected = 8'h00;
        alu_x_expected = 8'h00;

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