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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_tb.v] - Diff between revs 156 and 158
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| Rev 156 |
Rev 158 |
| Line 466... |
Line 466... |
alu_status_expected[V] = alu_a[6];
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alu_status_expected[V] = alu_a[6];
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alu_status_expected[N] = alu_a[7];
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alu_status_expected[N] = alu_a[7];
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check();
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check();
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end
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end
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// PHA
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alu_opcode = PHA_IMP;
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@(negedge clk);
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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alu_result_expected = DUT.A;
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check();
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// PHP
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alu_opcode = PHP_IMP;
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@(negedge clk);
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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alu_status_expected = DUT.STATUS;
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check();
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// BRK
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alu_opcode = BRK_IMP;
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@(negedge clk);
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alu_status_expected[B] = 1;
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check();
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// SEC
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// SEC
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alu_opcode = SEC_IMP;
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alu_opcode = SEC_IMP;
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@(negedge clk);
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@(negedge clk);
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alu_status_expected[C] = 1;
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alu_status_expected[C] = 1;
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check();
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check();
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