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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_tb.v] - Diff between revs 173 and 174

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Rev 173 Rev 174
Line 234... Line 234...
        alu_opcode = SBC_IMM;
        alu_opcode = SBC_IMM;
        for (i = 0; i < 1000; i = i + 1)
        for (i = 0; i < 1000; i = i + 1)
        begin
        begin
                alu_a = 1;
                alu_a = 1;
                @(negedge clk);
                @(negedge clk);
                $display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
                //$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
                $display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
                //$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
                $display("op1 = %d op2 = %d  c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
                //$display("op1 = %d op2 = %d  c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
                sign = alu_result_expected[7];
                sign = alu_result_expected[7];
                {alu_status_expected[C], alu_result_expected} = alu_result_expected - alu_a - ( 1 - alu_status_expected[C]);
                alu_result_expected = alu_result_expected - alu_a - ( 1 - alu_status_expected[C]);
 
                alu_status_expected[C] = ~alu_result_expected[7];
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                alu_status_expected[N] = alu_result_expected[7];
                $display("alu_a[7] = %b == sign = %b && alu_a[7] = %b != alu_result_expected[7] = %b", alu_a[7], sign, alu_a[7], alu_result_expected[7]);
                //$display("alu_a[7] = %b == sign = %b && alu_a[7] = %b != alu_result_expected[7] = %b", alu_a[7], sign, alu_a[7], alu_result_expected[7]);
                alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
                alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
                check;
                check;
        end
        end
 
 
        // LDA
        // LDA

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