URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_wrapper.v] - Diff between revs 126 and 129

Rev 126	Rev 129
Line 40...	Line 40...
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`////////////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////////////`

`include "timescale.v"	`include "timescale.v"
	`include "T6507LP_ALU.v"

`module wrapper_alu();`	`module t6507lp_alu_wrapper();`
`parameter [3:0] DATA_SIZE = 4'd8;`	`parameter [3:0] DATA_SIZE = 4'd8;`
`localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;`	`localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;`

`// all inputs are regs`	`// all inputs are regs`
`reg clk;`	`reg clk;`
`reg n_rst_i;`	`reg reset_n;`
`reg alu_enable;`	`reg alu_enable;`
`reg alu_opcode;`	`reg [DATA_SIZE_:0] alu_opcode;`
`reg alu_a;`	`reg [DATA_SIZE_:0] alu_a;`

`// all outputs are wires`	`// all outputs are wires`
`wire alu_result;`	`wire [DATA_SIZE_:0] alu_result;`
`wire alu_status;`	`wire [DATA_SIZE_:0] alu_status;`
`wire alu_x;`	`wire [DATA_SIZE_:0] alu_x;`
`wire alu_y;`	`wire [DATA_SIZE_:0] alu_y;`


`initial clk = 0;`	`initial clk = 0;`
`always #10 clk <= ~clk;`	`always #10 clk <= ~clk;`

	`//always #100 $write("working");`

`T6507LP_ALU T6507LP_ALU (`	`T6507LP_ALU T6507LP_ALU (`
`.clk_i (clk),`	`.clk_i (clk),`
`.n_rst_i (reset_n),`	`.n_rst_i (reset_n),`
`.alu_enable (alu_enable),`	`.alu_enable (alu_enable),`
`.alu_result (alu_result),`	`.alu_result (alu_result),`