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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "T6507LP_ALU.v"
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`include "t6507lp_alu.v"
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module t6507lp_alu_wrapper();
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module t6507lp_alu_wrapper();
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] DATA_SIZE = 4'd8;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
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// all inputs are regs
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// all inputs are regs
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reg clk;
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reg clk;
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reg reset_n;
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wire reset_n;
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reg alu_enable;
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wire alu_enable;
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reg [DATA_SIZE_:0] alu_opcode;
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wire [DATA_SIZE_:0] alu_opcode;
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reg [DATA_SIZE_:0] alu_a;
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wire [DATA_SIZE_:0] alu_a;
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// all outputs are wires
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// all outputs are wires
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wire [DATA_SIZE_:0] alu_result;
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wire [DATA_SIZE_:0] alu_result;
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wire [DATA_SIZE_:0] alu_status;
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wire [DATA_SIZE_:0] alu_status;
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wire [DATA_SIZE_:0] alu_x;
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wire [DATA_SIZE_:0] alu_x;
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wire [DATA_SIZE_:0] alu_y;
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wire [DATA_SIZE_:0] alu_y;
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initial clk = 0;
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initial clk = 0;
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always #10 clk <= ~clk;
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always #10 clk <= ~clk;
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//always #100 $write("working");
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always @(posedge clk) begin
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$display("reset is %b", reset_n);
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T6507LP_ALU T6507LP_ALU (
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$display("alu_enable is %b", alu_enable);
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.clk_i (clk),
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$display("alu_opcode is %h", alu_opcode);
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.n_rst_i (reset_n),
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$display("alu_a is %d", alu_a);
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end
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t6507lp_alu t6507lp_alu (
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.clk (clk),
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.reset_n (reset_n),
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.alu_enable (alu_enable),
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.alu_enable (alu_enable),
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.alu_result (alu_result),
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.alu_result (alu_result),
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.alu_status (alu_status),
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.alu_status (alu_status),
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.alu_opcode (alu_opcode),
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.alu_opcode (alu_opcode),
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.alu_a (alu_a),
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.alu_a (alu_a),
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