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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_wrapper.v] - Diff between revs 143 and 144
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Rev 144 |
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] DATA_SIZE = 4'd8;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
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// all inputs are regs
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// all inputs are regs
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reg clk;
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reg clk;
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wire reset_n;
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reg reset_n;
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wire alu_enable;
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reg alu_enable;
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wire [DATA_SIZE_:0] alu_opcode;
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reg [DATA_SIZE_:0] alu_opcode;
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wire [DATA_SIZE_:0] alu_a;
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reg [DATA_SIZE_:0] alu_a;
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// all outputs are wires
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// all outputs are wires
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wire [DATA_SIZE_:0] alu_result;
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wire [DATA_SIZE_:0] alu_result;
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wire [DATA_SIZE_:0] alu_status;
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wire [DATA_SIZE_:0] alu_status;
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wire [DATA_SIZE_:0] alu_x;
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wire [DATA_SIZE_:0] alu_x;
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