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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_wrapper.v] - Diff between revs 143 and 144

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Rev 143 Rev 144
Line 48... Line 48...
        parameter [3:0] DATA_SIZE = 4'd8;
        parameter [3:0] DATA_SIZE = 4'd8;
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
 
 
        // all inputs are regs
        // all inputs are regs
        reg clk;
        reg clk;
        wire reset_n;
        reg reset_n;
        wire alu_enable;
        reg alu_enable;
        wire [DATA_SIZE_:0] alu_opcode;
        reg [DATA_SIZE_:0] alu_opcode;
        wire [DATA_SIZE_:0] alu_a;
        reg [DATA_SIZE_:0] alu_a;
 
 
        // all outputs are wires
        // all outputs are wires
        wire [DATA_SIZE_:0] alu_result;
        wire [DATA_SIZE_:0] alu_result;
        wire [DATA_SIZE_:0] alu_status;
        wire [DATA_SIZE_:0] alu_status;
        wire [DATA_SIZE_:0] alu_x;
        wire [DATA_SIZE_:0] alu_x;

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