| Line 83... |
Line 83... |
localparam FETCH_OP_EVAL_BRANCH = 5'b01011;
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localparam FETCH_OP_EVAL_BRANCH = 5'b01011;
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localparam FETCH_OP_FIX_PC = 5'b01100;
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localparam FETCH_OP_FIX_PC = 5'b01100;
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localparam READ_FROM_POINTER = 5'b01101;
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localparam READ_FROM_POINTER = 5'b01101;
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localparam READ_FROM_POINTER_X = 5'b01110;
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localparam READ_FROM_POINTER_X = 5'b01110;
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localparam READ_FROM_POINTER_X1 = 5'b01111;
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localparam READ_FROM_POINTER_X1 = 5'b01111;
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localparam PUSH_PCH = 5'b10000;
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localparam PUSH_PCL = 5'b10001;
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localparam PUSH_STATUS = 5'b10010;
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localparam FETCH_PCL = 5'b10011;
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localparam FETCH_PCH = 5'b10100;
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localparam RESET = 5'b11111;
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localparam RESET = 5'b11111;
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// OPCODES TODO: verify how this get synthesised
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// OPCODES TODO: verify how this get synthesised
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`include "../T6507LP_Package.v"
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`include "../T6507LP_Package.v"
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| Line 94... |
Line 99... |
// control signals
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// control signals
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localparam MEM_READ = 1'b0;
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localparam MEM_READ = 1'b0;
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localparam MEM_WRITE = 1'b1;
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localparam MEM_WRITE = 1'b1;
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reg [ADDR_SIZE_:0] pc; // program counter
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reg [ADDR_SIZE_:0] pc; // program counter
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reg [ADDR_SIZE_:0] sp; // stack pointer
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reg [DATA_SIZE:0] sp; // stack pointer. 9 bits wide.
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reg [DATA_SIZE_:0] ir; // instruction register
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reg [DATA_SIZE_:0] ir; // instruction register
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reg [ADDR_SIZE_:0] temp_addr; // temporary address
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reg [ADDR_SIZE_:0] temp_addr; // temporary address
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reg [DATA_SIZE_:0] temp_data; // temporary data
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reg [DATA_SIZE_:0] temp_data; // temporary data
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reg [4:0] state, next_state; // current and next state registers
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reg [4:0] state, next_state; // current and next state registers
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// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
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// TODO: not sure if this will be 5 bits wide. as of march 24th this was 5bit wide.
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// wiring that simplifies the FSM logic
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// wiring that simplifies the FSM logic by simplifying the addressing modes
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reg absolute;
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reg absolute;
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reg absolute_indexed;
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reg absolute_indexed;
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reg accumulator;
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reg accumulator;
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reg immediate;
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reg immediate;
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reg implied;
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reg implied;
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| Line 122... |
Line 127... |
reg read_modify_write;
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reg read_modify_write;
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reg write;
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reg write;
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reg jump;
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reg jump;
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reg jump_indirect;
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reg jump_indirect;
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// regs for the special instructions
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reg break;
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wire [ADDR_SIZE_:0] next_pc;
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wire [ADDR_SIZE_:0] next_pc;
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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reg page_crossed; // so the simple assign was changed into a combinational always block
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reg page_crossed; // so the simple assign was changed into a combinational always block
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| Line 192... |
Line 200... |
end
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end
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else begin
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else begin
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state <= next_state;
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state <= next_state;
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case (state)
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case (state)
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RESET: begin
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RESET: begin // The processor was reset
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// The processor was reset
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$write("under reset");
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$write("under reset");
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end
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end
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FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
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/*
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// the last cycle was a memory write.
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FETCH_OP: executed when the processor was reset or the last instruction could not fetch.
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FETCH_OP_CALC: enables the alu and fetchs the next instruction opcode. (pipelining)
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FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)
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*/
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FETCH_OP, FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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control <= MEM_READ;
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ir <= data_in;
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ir <= data_in;
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end
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end
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FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
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/*
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pc <= next_pc;
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in this state the opcode is already known so truly execution begins.
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address <= next_pc;
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all instruction execute this cycle.
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control <= MEM_READ;
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*/
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ir <= data_in;
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FETCH_LOW: begin
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end
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FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
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if (accumulator || implied) begin
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if (accumulator || implied) begin
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pc <= pc; // is this better?
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pc <= pc; // is this better?
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address <= pc;
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address <= pc;
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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| Line 255... |
Line 264... |
address <= data_in;
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address <= data_in;
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temp_data <= data_in;
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temp_data <= data_in;
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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else begin // the special instructions will fall here: BRK, RTI, RTS...
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else begin // the special instructions will fall here: BRK, RTI, RTS...
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if (break) begin
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pc <= next_pc;
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address <= sp;
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data_out <= {{3{1'b0}}, pc[12:8]};
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control <= MEM_WRITE;
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sp <= sp_minus_one;
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end
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end
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end
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end
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end
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FETCH_HIGH_CALC_INDEX: begin
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FETCH_HIGH_CALC_INDEX: begin
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pc <= next_pc;
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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temp_addr[12:8] <= data_in[4:0];
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address <= {data_in[4:0], address_plus_index[7:0]};
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address <= {data_in[4:0], address_plus_index[7:0]};
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control <= MEM_READ;
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control <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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// this cycle fetchs the next operand while still evaluating if a branch occurred.
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FETCH_OP_EVAL_BRANCH: begin
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FETCH_OP_EVAL_BRANCH: begin
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if (branch) begin
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if (branch) begin
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pc <= {{5{1'b0}}, address_plus_index[7:0]};
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pc <= {{5{1'b0}}, address_plus_index[7:0]};
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address <= {{5{1'b0}}, address_plus_index[7:0]};
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address <= {{5{1'b0}}, address_plus_index[7:0]};
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control <= MEM_READ;
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control <= MEM_READ;
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| Line 280... |
Line 296... |
control <= MEM_READ;
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control <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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ir <= data_in;
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ir <= data_in;
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end
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end
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end
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end
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// sometimes when reading memory page crosses may occur. the pc register must be fixed, i.e., add 16'h0100
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FETCH_OP_FIX_PC: begin
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FETCH_OP_FIX_PC: begin
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if (page_crossed) begin
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if (page_crossed) begin
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pc[12:8] <= address_plus_index[12:8];
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pc[12:8] <= address_plus_index[12:8];
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address[12:8] <= address_plus_index[12:8];
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address[12:8] <= address_plus_index[12:8];
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end
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end
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| Line 292... |
Line 309... |
address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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control <= MEM_READ;
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ir <= data_in;
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ir <= data_in;
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end
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end
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end
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end
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// several instructions ocupy 3 bytes in memory. this cycle reads the third byte.
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FETCH_HIGH: begin
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FETCH_HIGH: begin
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if (jump) begin
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if (jump) begin
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pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
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pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
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address <= {data_in[4:0], temp_addr[7:0]};
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address <= {data_in[4:0], temp_addr[7:0]};
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control <= MEM_READ;
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control <= MEM_READ;
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| Line 438... |
Line 456... |
address <= address_plus_index;
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address <= address_plus_index;
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temp_addr[12:8] <= data_in;
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temp_addr[12:8] <= data_in;
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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end
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end
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PUSH_PCH: begin
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pc <= pc;
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address <= sp;
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data_out <= pc[7:0];
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control <= MEM_WRITE;
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sp <= sp_minus_one;
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end
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PUSH_PCL: begin
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pc <= pc;
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address <= sp;
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data_out <= alu_status;
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control <= MEM_WRITE;
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sp <= sp_minus_one;
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end
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PUSH_STATUS: begin
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address <= 13'hFFFE;
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control <= MEM_READ;
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end
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FETCH_PCL: begin
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pc[7:0] <= data_in;
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address <= 13'hFFFF;
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control <= MEM_READ;
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end
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FETCH_PCH: begin
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pc[12:8] <= data_in[4:0];
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address <= {data_in[4:0], pc[7:0]};
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control <= MEM_READ;
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end
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default: begin
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default: begin
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$finish(0);
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$finish(0);
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end
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end
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| Line 517... |
Line 563... |
end
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end
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else if (indirectx || indirecty) begin
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else if (indirectx || indirecty) begin
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next_state = READ_FROM_POINTER;
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next_state = READ_FROM_POINTER;
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end
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end
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else begin // all the special instructions will fall here
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else begin // all the special instructions will fall here
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next_state = RESET;
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if (break) begin
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next_state = PUSH_PCH;
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end
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end
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end
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end
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end
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READ_FROM_POINTER: begin
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READ_FROM_POINTER: begin
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if (indirectx) begin
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if (indirectx) begin
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next_state = READ_FROM_POINTER_X;
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next_state = READ_FROM_POINTER_X;
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| Line 639... |
Line 687... |
next_state = WRITE_MEM;
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next_state = WRITE_MEM;
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end
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end
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WRITE_MEM: begin
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WRITE_MEM: begin
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next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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PUSH_PCH: begin
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next_state = PUSH_PCL;
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end
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PUSH_PCL: begin
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next_state = PUSH_STATUS;
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end
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PUSH_STATUS: begin
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next_state = FETCH_PCL;
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end
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FETCH_PCL: begin
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next_state = FETCH_PCH;
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end
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FETCH_PCH: begin
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next_state = FETCH_OP;
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end
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default: begin
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default: begin
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next_state = RESET;
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next_state = RESET;
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end
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end
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endcase
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endcase
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end
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end
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| Line 667... |
Line 730... |
write = 1'b0;
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write = 1'b0;
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jump = 1'b0;
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jump = 1'b0;
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jump_indirect = 1'b0;
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jump_indirect = 1'b0;
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branch = 1'b0;
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branch = 1'b0;
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break = 1'b0;
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case (ir)
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case (ir)
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CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
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CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
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PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
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PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
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implied = 1'b1;
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implied = 1'b1;
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end
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end
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| Line 808... |
Line 873... |
end
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end
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JMP_IND: begin
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JMP_IND: begin
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jump_indirect = 1'b1;
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jump_indirect = 1'b1;
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end
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end
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BRK_IMP: begin
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BRK_IMP: begin
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// something goes in here
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break = 1'b1;
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end
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end
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default: begin
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default: begin
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$write("state : %b", state);
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$write("state : %b", state);
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if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
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if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
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$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
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$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
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