| Line 88... |
Line 88... |
localparam PUSH_PCH = 5'b10000;
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localparam PUSH_PCH = 5'b10000;
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localparam PUSH_PCL = 5'b10001;
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localparam PUSH_PCL = 5'b10001;
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localparam PUSH_STATUS = 5'b10010;
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localparam PUSH_STATUS = 5'b10010;
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localparam FETCH_PCL = 5'b10011;
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localparam FETCH_PCL = 5'b10011;
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localparam FETCH_PCH = 5'b10100;
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localparam FETCH_PCH = 5'b10100;
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localparam INCREMENT_SP = 5'b10101;
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localparam PULL_STATUS = 5'b10110;
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localparam PULL_PCL = 5'b10111;
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localparam PULL_PCH = 5'b11000;
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localparam RESET = 5'b11111;
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localparam RESET = 5'b11111;
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// OPCODES TODO: verify how this get synthesised
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// OPCODES TODO: verify how this get synthesised
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`include "../T6507LP_Package.v"
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`include "../T6507LP_Package.v"
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| Line 129... |
Line 133... |
reg jump;
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reg jump;
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reg jump_indirect;
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reg jump_indirect;
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// regs for the special instructions
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// regs for the special instructions
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reg break;
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reg break;
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reg rti;
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wire [ADDR_SIZE_:0] next_pc;
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wire [ADDR_SIZE_:0] next_pc;
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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| Line 271... |
Line 276... |
address <= sp;
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address <= sp;
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data_out <= {{3{1'b0}}, pc[12:8]};
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data_out <= {{3{1'b0}}, pc[12:8]};
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control <= MEM_WRITE;
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control <= MEM_WRITE;
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sp <= sp_minus_one;
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sp <= sp_minus_one;
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end
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end
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else if (rti) begin
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address <= sp;
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control <= MEM_READ;
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end
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end
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end
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end
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end
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FETCH_HIGH_CALC_INDEX: begin
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FETCH_HIGH_CALC_INDEX: begin
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pc <= next_pc;
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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temp_addr[12:8] <= data_in[4:0];
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| Line 484... |
Line 493... |
FETCH_PCH: begin
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FETCH_PCH: begin
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pc[12:8] <= data_in[4:0];
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pc[12:8] <= data_in[4:0];
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address <= {data_in[4:0], pc[7:0]};
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address <= {data_in[4:0], pc[7:0]};
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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INCREMENT_SP: begin
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sp <= sp_plus_one;
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address <= sp_plus_one;
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end
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PULL_STATUS: begin
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sp <= sp_plus_one;
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address <= sp_plus_one;
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temp_data <= data_in;
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end
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PULL_PCL: begin
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sp <= sp_plus_one;
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address <= sp_plus_one;
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pc[7:0] <= data_in;
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end
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PULL_PCH: begin
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pc[12:8] <= data_in[4:0];
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address <= {data_in[4:0], pc[7:0]};
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end
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default: begin
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default: begin
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$finish(0);
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$finish(0);
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end
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end
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| Line 566... |
Line 593... |
end
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end
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else begin // all the special instructions will fall here
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else begin // all the special instructions will fall here
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if (break) begin
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if (break) begin
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next_state = PUSH_PCH;
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next_state = PUSH_PCH;
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end
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end
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else if (rti) begin
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next_state = INCREMENT_SP;
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end
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end
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end
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end
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end
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READ_FROM_POINTER: begin
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READ_FROM_POINTER: begin
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if (indirectx) begin
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if (indirectx) begin
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next_state = READ_FROM_POINTER_X;
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next_state = READ_FROM_POINTER_X;
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| Line 702... |
Line 732... |
next_state = FETCH_PCH;
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next_state = FETCH_PCH;
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end
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end
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FETCH_PCH: begin
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FETCH_PCH: begin
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next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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INCREMENT_SP: begin
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next_state = PULL_STATUS;
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end
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PULL_STATUS: begin
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next_state = PULL_PCL;
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end
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PULL_PCL: begin
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next_state = PULL_PCH;
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alu_opcode = ir;
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alu_enable = 1'b1;
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alu_a = temp_data;
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end
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PULL_PCH: begin
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next_state = FETCH_OP;
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end
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default: begin
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default: begin
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next_state = RESET;
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next_state = RESET;
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end
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end
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endcase
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endcase
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end
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end
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| Line 731... |
Line 776... |
jump = 1'b0;
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jump = 1'b0;
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jump_indirect = 1'b0;
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jump_indirect = 1'b0;
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branch = 1'b0;
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branch = 1'b0;
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break = 1'b0;
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break = 1'b0;
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rti = 1'b0;
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case (ir)
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case (ir)
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CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
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CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
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PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
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PLP_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
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implied = 1'b1;
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implied = 1'b1;
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end
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end
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ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
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ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
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accumulator = 1'b1;
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accumulator = 1'b1;
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end
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end
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| Line 875... |
Line 921... |
jump_indirect = 1'b1;
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jump_indirect = 1'b1;
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end
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end
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BRK_IMP: begin
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BRK_IMP: begin
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break = 1'b1;
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break = 1'b1;
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end
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end
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RTI_IMP: begin
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rti = 1'b1;
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end
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default: begin
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default: begin
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$write("state : %b", state);
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$write("state : %b", state);
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if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
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if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
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$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
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$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
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$finish();
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$finish();
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