| Line 94... |
Line 94... |
localparam PULL_STATUS = 5'b10110;
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localparam PULL_STATUS = 5'b10110;
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localparam PULL_PCL = 5'b10111;
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localparam PULL_PCL = 5'b10111;
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localparam PULL_PCH = 5'b11000;
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localparam PULL_PCH = 5'b11000;
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localparam INCREMENT_PC = 5'b11001;
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localparam INCREMENT_PC = 5'b11001;
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localparam PUSH_REGISTER = 5'b11010;
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localparam PUSH_REGISTER = 5'b11010;
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localparam PULL_REGISTER = 5'b11011;
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localparam RESET = 5'b11111;
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localparam RESET = 5'b11111;
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// OPCODES TODO: verify how this get synthesised
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// OPCODES TODO: verify how this get synthesised
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`include "../T6507LP_Package.v"
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`include "../T6507LP_Package.v"
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| Line 139... |
Line 140... |
reg break;
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reg break;
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reg rti;
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reg rti;
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reg rts;
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reg rts;
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reg pha;
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reg pha;
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reg php;
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reg php;
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reg pla;
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reg plp;
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wire [ADDR_SIZE_:0] next_pc;
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wire [ADDR_SIZE_:0] next_pc;
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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| Line 291... |
Line 294... |
pc <= pc;
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pc <= pc;
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address <= sp;
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address <= sp;
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data_out <= (pha) ? alu_result : alu_status;
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data_out <= (pha) ? alu_result : alu_status;
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control <= MEM_WRITE;
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control <= MEM_WRITE;
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end
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end
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else if (pla || plp) begin
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pc <= pc;
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address <= sp;
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control <= MEM_READ;
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end
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end
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end
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end
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end
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FETCH_HIGH_CALC_INDEX: begin
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FETCH_HIGH_CALC_INDEX: begin
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pc <= next_pc;
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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temp_addr[12:8] <= data_in[4:0];
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| Line 531... |
Line 539... |
PUSH_REGISTER: begin
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PUSH_REGISTER: begin
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pc <= pc;
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pc <= pc;
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address <= pc;
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address <= pc;
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sp <= sp_minus_one;
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sp <= sp_minus_one;
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control <= MEM_READ;
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control <= MEM_READ;
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temp_data <= data_in;
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end
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PULL_REGISTER: begin
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pc <= pc;
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address <= pc;
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temp_data <= data_in;
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end
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end
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default: begin
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default: begin
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$finish(0);
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$finish(0);
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end
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end
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| Line 626... |
Line 640... |
next_state = PUSH_REGISTER;
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next_state = PUSH_REGISTER;
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end
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end
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else if (php) begin
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else if (php) begin
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next_state = PUSH_REGISTER;
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next_state = PUSH_REGISTER;
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end
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end
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else if (pla || plp) begin
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next_state = INCREMENT_SP;
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end
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end
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end
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end
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end
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READ_FROM_POINTER: begin
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READ_FROM_POINTER: begin
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if (indirectx) begin
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if (indirectx) begin
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next_state = READ_FROM_POINTER_X;
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next_state = READ_FROM_POINTER_X;
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| Line 766... |
Line 783... |
end
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end
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INCREMENT_SP: begin
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INCREMENT_SP: begin
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if (rti) begin
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if (rti) begin
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next_state = PULL_STATUS;
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next_state = PULL_STATUS;
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end
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end
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else if (pla || plp) begin
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next_state = PULL_REGISTER;
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end
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else begin // rts
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else begin // rts
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next_state = PULL_PCL;
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next_state = PULL_PCL;
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end
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end
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end
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end
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PULL_STATUS: begin
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PULL_STATUS: begin
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| Line 793... |
Line 813... |
next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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PUSH_REGISTER: begin
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PUSH_REGISTER: begin
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next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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PULL_REGISTER: begin
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next_state = FETCH_OP_CALC_PARAM;
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end
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default: begin
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default: begin
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next_state = RESET;
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next_state = RESET;
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end
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end
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endcase
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endcase
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end
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end
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| Line 826... |
Line 849... |
break = 1'b0;
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break = 1'b0;
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rti = 1'b0;
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rti = 1'b0;
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rts = 1'b0;
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rts = 1'b0;
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pha = 1'b0;
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pha = 1'b0;
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php = 1'b0;
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php = 1'b0;
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pla = 1'b0;
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plp = 1'b0;
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case (ir)
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case (ir)
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CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP,
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CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP,
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SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
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SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
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implied = 1'b1;
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implied = 1'b1;
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| Line 982... |
Line 1007... |
pha = 1'b1;
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pha = 1'b1;
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end
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end
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PHP_IMP: begin
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PHP_IMP: begin
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php = 1'b1;
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php = 1'b1;
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end
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end
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PLA_IMP: begin
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pla = 1'b1;
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end
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PLP_IMP: begin
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plp = 1'b1;
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end
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default: begin
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default: begin
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$write("state : %b", state);
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$write("state : %b", state);
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if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
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if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
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$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
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$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
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$finish();
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$finish();
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