| Line 8... |
Line 8... |
//// Description ////
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//// Description ////
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//// 6507 FSM ////
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//// 6507 FSM ////
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//// ////
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//// ////
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//// TODO: ////
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//// TODO: ////
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//// - Fix relative mode, bit 7 means negative ////
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//// - Fix relative mode, bit 7 means negative ////
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//// - Code the indirect indexed mode ////
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//// - Comment the code ////
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//// - Code the absolute indirect mode ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// ////
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//// ////
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| Line 57... |
Line 56... |
input reset_n;
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input reset_n;
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input [DATA_SIZE_:0] alu_result;
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input [DATA_SIZE_:0] alu_result;
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input [DATA_SIZE_:0] alu_status;
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input [DATA_SIZE_:0] alu_status;
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input [DATA_SIZE_:0] data_in;
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input [DATA_SIZE_:0] data_in;
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output reg [ADDR_SIZE_:0] address;
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output reg [ADDR_SIZE_:0] address;
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output reg control; // one bit is enough? read = 0, write = 1
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output reg control; // read = 0, write = 1
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output reg [DATA_SIZE_:0] data_out;
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output reg [DATA_SIZE_:0] data_out;
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output reg [DATA_SIZE_:0] alu_opcode;
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output reg [DATA_SIZE_:0] alu_opcode;
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output reg [DATA_SIZE_:0] alu_a;
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output reg [DATA_SIZE_:0] alu_a;
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output reg alu_enable;
|
output reg alu_enable;
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|
|
input [DATA_SIZE_:0] alu_x;
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input [DATA_SIZE_:0] alu_x;
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input [DATA_SIZE_:0] alu_y;
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input [DATA_SIZE_:0] alu_y;
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|
|
// FSM states
|
// FSM states
|
localparam FETCH_OP = 5'b00000;
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localparam FETCH_OP = 5'b00000;
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localparam FETCH_OP_CALC = 5'b00001;
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//localparam FETCH_OP_CALC = 5'b00001; this was never used
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localparam FETCH_LOW = 5'b00010;
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localparam FETCH_LOW = 5'b00010;
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localparam FETCH_HIGH = 5'b00011;
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localparam FETCH_HIGH = 5'b00011;
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localparam READ_MEM = 5'b00100;
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localparam READ_MEM = 5'b00100;
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localparam DUMMY_WRT_CALC = 5'b00101;
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localparam DUMMY_WRT_CALC = 5'b00101;
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localparam WRITE_MEM = 5'b00110;
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localparam WRITE_MEM = 5'b00110;
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| Line 95... |
Line 94... |
localparam PULL_PCL = 5'b10111;
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localparam PULL_PCL = 5'b10111;
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localparam PULL_PCH = 5'b11000;
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localparam PULL_PCH = 5'b11000;
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localparam INCREMENT_PC = 5'b11001;
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localparam INCREMENT_PC = 5'b11001;
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localparam PUSH_REGISTER = 5'b11010;
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localparam PUSH_REGISTER = 5'b11010;
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localparam PULL_REGISTER = 5'b11011;
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localparam PULL_REGISTER = 5'b11011;
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localparam DUMMY = 5'b11100;
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|
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localparam RESET = 5'b11111;
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localparam RESET = 5'b11111;
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|
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// OPCODES TODO: verify how this get synthesised
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// OPCODES TODO: verify how this get synthesised
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`include "../T6507LP_Package.v"
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`include "../T6507LP_Package.v"
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| Line 112... |
Line 112... |
reg [DATA_SIZE_:0] ir; // instruction register
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reg [DATA_SIZE_:0] ir; // instruction register
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reg [ADDR_SIZE_:0] temp_addr; // temporary address
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reg [ADDR_SIZE_:0] temp_addr; // temporary address
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reg [DATA_SIZE_:0] temp_data; // temporary data
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reg [DATA_SIZE_:0] temp_data; // temporary data
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|
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reg [4:0] state, next_state; // current and next state registers
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reg [4:0] state, next_state; // current and next state registers
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// TODO: not sure if this will be 5 bits wide. as of march 24th this was 5bit wide.
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|
|
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// wiring that simplifies the FSM logic by simplifying the addressing modes
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// wiring that simplifies the FSM logic by simplifying the addressing modes
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reg absolute;
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reg absolute;
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reg absolute_indexed;
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reg absolute_indexed;
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reg accumulator;
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reg accumulator;
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| Line 142... |
Line 141... |
reg rts;
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reg rts;
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reg pha;
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reg pha;
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reg php;
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reg php;
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reg pla;
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reg pla;
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reg plp;
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reg plp;
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reg jsr;
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|
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wire [ADDR_SIZE_:0] next_pc;
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wire [ADDR_SIZE_:0] next_pc;
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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|
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reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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| Line 218... |
Line 218... |
RESET: begin // The processor was reset
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RESET: begin // The processor was reset
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$write("under reset");
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$write("under reset");
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end
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end
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/*
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/*
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FETCH_OP: executed when the processor was reset or the last instruction could not fetch.
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FETCH_OP: executed when the processor was reset or the last instruction could not fetch.
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FETCH_OP_CALC: enables the alu and fetchs the next instruction opcode. (pipelining)
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FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)
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FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)
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*/
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*/
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FETCH_OP, FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
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FETCH_OP, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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control <= MEM_READ;
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ir <= data_in;
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ir <= data_in;
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end
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end
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| Line 282... |
Line 281... |
if (break) begin
|
if (break) begin
|
pc <= next_pc;
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pc <= next_pc;
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address <= sp;
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address <= sp;
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data_out <= {{3{1'b0}}, pc[12:8]};
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data_out <= {{3{1'b0}}, pc[12:8]};
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control <= MEM_WRITE;
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control <= MEM_WRITE;
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sp <= sp_minus_one;
|
|
end
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end
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else if (rti || rts) begin
|
else if (rti || rts) begin
|
address <= sp;
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address <= sp;
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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| Line 299... |
Line 297... |
else if (pla || plp) begin
|
else if (pla || plp) begin
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pc <= pc;
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pc <= pc;
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address <= sp;
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address <= sp;
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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else begin // jsr
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address <= sp;
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control <= MEM_READ;
|
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temp_addr <= {{5{1'b0}}, data_in};
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pc <= next_pc;
|
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end
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end
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end
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end
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end
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FETCH_HIGH_CALC_INDEX: begin
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FETCH_HIGH_CALC_INDEX: begin
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pc <= next_pc;
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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temp_addr[12:8] <= data_in[4:0];
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| Line 361... |
Line 365... |
address <= {data_in[4:0],temp_addr[7:0]};
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address <= {data_in[4:0],temp_addr[7:0]};
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control <= MEM_READ;
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control <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
|
end
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end
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end
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end
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//else begin
|
|
// $write("FETCHHIGH PROBLEM");
|
|
// $finish(0);
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|
//end
|
|
end
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end
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READ_MEM: begin
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READ_MEM: begin
|
if (read_modify_write) begin
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if (read_modify_write) begin
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pc <= pc;
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pc <= pc;
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address <= temp_addr;
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address <= temp_addr;
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| Line 383... |
Line 383... |
control <= MEM_READ;
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control <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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end
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end
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READ_MEM_CALC_INDEX: begin
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READ_MEM_CALC_INDEX: begin
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//pc <= next_pc; // pc was already updated in the previous cycle
|
|
address <= address_plus_index;
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address <= address_plus_index;
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temp_addr <= address_plus_index;
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temp_addr <= address_plus_index;
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|
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if (write) begin
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if (write) begin
|
control <= MEM_WRITE;
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control <= MEM_WRITE;
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| Line 486... |
Line 485... |
control <= MEM_READ;
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control <= MEM_READ;
|
end
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end
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end
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end
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PUSH_PCH: begin
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PUSH_PCH: begin
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pc <= pc;
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pc <= pc;
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address <= sp;
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address <= sp_minus_one;
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data_out <= pc[7:0];
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data_out <= pc[7:0];
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control <= MEM_WRITE;
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control <= MEM_WRITE;
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sp <= sp_minus_one;
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sp <= sp_minus_one;
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end
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end
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PUSH_PCL: begin
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PUSH_PCL: begin
|
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if (jsr) begin
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pc <= pc;
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pc <= pc;
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address <= sp;
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address <= pc;
|
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control <= MEM_READ;
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sp <= sp_minus_one;
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end
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else begin
|
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pc <= pc;
|
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address <= sp_minus_one;
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data_out <= alu_status;
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data_out <= alu_status;
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control <= MEM_WRITE;
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control <= MEM_WRITE;
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sp <= sp_minus_one;
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sp <= sp_minus_one;
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end
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end
|
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end
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PUSH_STATUS: begin
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PUSH_STATUS: begin
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address <= 13'hFFFE;
|
address <= 13'hFFFE;
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control <= MEM_READ;
|
control <= MEM_READ;
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end
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end
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FETCH_PCL: begin
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FETCH_PCL: begin
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| Line 546... |
Line 553... |
PULL_REGISTER: begin
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PULL_REGISTER: begin
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pc <= pc;
|
pc <= pc;
|
address <= pc;
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address <= pc;
|
temp_data <= data_in;
|
temp_data <= data_in;
|
end
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end
|
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DUMMY: begin
|
|
address <= sp;
|
|
control <= MEM_WRITE;
|
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end
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default: begin
|
default: begin
|
$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
|
$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
|
$finish(0);
|
$finish(0);
|
end
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end
|
|
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| Line 559... |
Line 570... |
|
|
always @ (*) begin // this is the next_state logic and the output logic always block
|
always @ (*) begin // this is the next_state logic and the output logic always block
|
alu_opcode = 8'h00;
|
alu_opcode = 8'h00;
|
alu_a = 8'h00;
|
alu_a = 8'h00;
|
alu_enable = 1'b0;
|
alu_enable = 1'b0;
|
|
next_state = RESET; // these lines prevents latches
|
next_state = RESET; // this prevents the latch
|
|
|
|
case (state)
|
case (state)
|
RESET: begin
|
RESET: begin
|
next_state = FETCH_OP;
|
next_state = FETCH_OP;
|
end
|
end
|
FETCH_OP: begin
|
FETCH_OP: begin
|
next_state = FETCH_LOW;
|
next_state = FETCH_LOW;
|
end
|
end
|
//FETCH_OP_CALC: begin // so far no addressing mode required the use of this state
|
|
// next_state = FETCH_LOW;
|
|
// alu_opcode = ir;
|
|
// alu_enable = 1'b1;
|
|
//end
|
|
FETCH_OP_CALC_PARAM: begin
|
FETCH_OP_CALC_PARAM: begin
|
next_state = FETCH_LOW;
|
next_state = FETCH_LOW;
|
alu_opcode = ir;
|
alu_opcode = ir;
|
alu_enable = 1'b1;
|
alu_enable = 1'b1;
|
alu_a = temp_data;
|
alu_a = temp_data;
|
| Line 607... |
Line 612... |
end
|
end
|
end
|
end
|
else if (zero_page_indexed) begin
|
else if (zero_page_indexed) begin
|
next_state = READ_MEM_CALC_INDEX;
|
next_state = READ_MEM_CALC_INDEX;
|
end
|
end
|
else if (absolute || jump_indirect) begin // at least the absolute address mode falls here
|
else if (absolute || jump_indirect) begin
|
next_state = FETCH_HIGH;
|
next_state = FETCH_HIGH;
|
if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly
|
if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly
|
alu_opcode = ir;
|
alu_opcode = ir;
|
alu_enable = 1'b1;
|
alu_enable = 1'b1;
|
alu_a = 8'h00;
|
alu_a = 8'h00;
|
| Line 643... |
Line 648... |
next_state = PUSH_REGISTER;
|
next_state = PUSH_REGISTER;
|
end
|
end
|
else if (pla || plp) begin
|
else if (pla || plp) begin
|
next_state = INCREMENT_SP;
|
next_state = INCREMENT_SP;
|
end
|
end
|
|
else begin // jsr
|
|
next_state = DUMMY;
|
|
end
|
end
|
end
|
end
|
end
|
READ_FROM_POINTER: begin
|
READ_FROM_POINTER: begin
|
if (indirectx) begin
|
if (indirectx) begin
|
next_state = READ_FROM_POINTER_X;
|
next_state = READ_FROM_POINTER_X;
|
| Line 664... |
Line 672... |
end
|
end
|
else if (indirecty) begin
|
else if (indirecty) begin
|
next_state = READ_MEM_FIX_ADDR;
|
next_state = READ_MEM_FIX_ADDR;
|
end
|
end
|
else begin
|
else begin
|
if (read) begin // read_modify_write was showing up here for no reason. no instruction using pointers is from that type.
|
if (read) begin // no instruction using pointers is from type read_modify_write
|
next_state = READ_MEM;
|
next_state = READ_MEM;
|
end
|
end
|
else if (write) begin
|
else if (write) begin
|
alu_opcode = ir;
|
alu_opcode = ir;
|
alu_enable = 1'b1;
|
alu_enable = 1'b1;
|
| Line 768... |
Line 776... |
end
|
end
|
PUSH_PCH: begin
|
PUSH_PCH: begin
|
next_state = PUSH_PCL;
|
next_state = PUSH_PCL;
|
end
|
end
|
PUSH_PCL: begin
|
PUSH_PCL: begin
|
|
if (jsr) begin
|
|
next_state = FETCH_HIGH;
|
|
end
|
|
else begin
|
next_state = PUSH_STATUS;
|
next_state = PUSH_STATUS;
|
end
|
end
|
|
end
|
PUSH_STATUS: begin
|
PUSH_STATUS: begin
|
next_state = FETCH_PCL;
|
next_state = FETCH_PCL;
|
end
|
end
|
FETCH_PCL: begin
|
FETCH_PCL: begin
|
next_state = FETCH_PCH;
|
next_state = FETCH_PCH;
|
| Line 816... |
Line 829... |
next_state = FETCH_OP;
|
next_state = FETCH_OP;
|
end
|
end
|
PULL_REGISTER: begin
|
PULL_REGISTER: begin
|
next_state = FETCH_OP_CALC_PARAM;
|
next_state = FETCH_OP_CALC_PARAM;
|
end
|
end
|
|
DUMMY: begin
|
|
next_state = PUSH_PCH;
|
|
end
|
default: begin
|
default: begin
|
next_state = RESET;
|
next_state = RESET;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
| Line 851... |
Line 867... |
rts = 1'b0;
|
rts = 1'b0;
|
pha = 1'b0;
|
pha = 1'b0;
|
php = 1'b0;
|
php = 1'b0;
|
pla = 1'b0;
|
pla = 1'b0;
|
plp = 1'b0;
|
plp = 1'b0;
|
|
jsr = 1'b0;
|
|
|
case (ir)
|
case (ir)
|
CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP,
|
CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP,
|
SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
|
SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
|
implied = 1'b1;
|
implied = 1'b1;
|
| Line 964... |
Line 981... |
end
|
end
|
else begin
|
else begin
|
branch = 1'b0;
|
branch = 1'b0;
|
end
|
end
|
end
|
end
|
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JSR_ABS, LDA_ABS,
|
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, LDA_ABS,
|
LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
|
LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
|
absolute = 1'b1;
|
absolute = 1'b1;
|
end
|
end
|
ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
|
ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
|
SBC_ABX, STA_ABX: begin
|
SBC_ABX, STA_ABX: begin
|
| Line 1013... |
Line 1030... |
pla = 1'b1;
|
pla = 1'b1;
|
end
|
end
|
PLP_IMP: begin
|
PLP_IMP: begin
|
plp = 1'b1;
|
plp = 1'b1;
|
end
|
end
|
|
JSR_ABS: begin
|
|
jsr = 1'b1;
|
|
end
|
default: begin
|
default: begin
|
$write("state : %b", state);
|
$write("state : %b", state);
|
if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
|
if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
|
$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
|
$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
|
$finish();
|
$finish();
|
