| Line 43... |
Line 43... |
//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
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module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, mem_rw, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] ADDR_SIZE = 4'd13;
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parameter [3:0] ADDR_SIZE = 4'd13;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
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input clk;
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input clk; // master clock
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input reset_n;
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input reset_n; // active low reset
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input [DATA_SIZE_:0] alu_result;
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input [DATA_SIZE_:0] alu_result; // result from alu operation
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input [DATA_SIZE_:0] alu_status;
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input [DATA_SIZE_:0] alu_status; // alu status register
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input [DATA_SIZE_:0] data_in;
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input [DATA_SIZE_:0] data_in; // data that comes from the bus controller
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output reg [ADDR_SIZE_:0] address;
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output reg [ADDR_SIZE_:0] address; // system bus address
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output reg control; // read = 0, write = 1
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output reg mem_rw; // read = 0, write = 1
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output reg [DATA_SIZE_:0] data_out;
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output reg [DATA_SIZE_:0] data_out; // data that will be written somewhere else
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output reg [DATA_SIZE_:0] alu_opcode;
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output reg [DATA_SIZE_:0] alu_opcode; // current opcode
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output reg [DATA_SIZE_:0] alu_a;
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output reg [DATA_SIZE_:0] alu_a; // extra operand sent to the alu
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output reg alu_enable;
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output reg alu_enable; // a flag that when high tells the alu when to perform the operations
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input [DATA_SIZE_:0] alu_x;
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input [DATA_SIZE_:0] alu_x;
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input [DATA_SIZE_:0] alu_y;
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input [DATA_SIZE_:0] alu_y;
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// FSM states. If aiming for less power consumption try gray coding.
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// FSM states. If aiming for less power consumption try gray coding.
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localparam FETCH_OP = 5'b00000;
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//localparam FETCH_OP_CALC = 5'b00001; this was never used
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//localparam FETCH_OP_CALC = 5'b00001; this was never used
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localparam FETCH_OP = 5'b00000;
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localparam FETCH_LOW = 5'b00010;
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localparam FETCH_LOW = 5'b00010;
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localparam FETCH_HIGH = 5'b00011;
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localparam FETCH_HIGH = 5'b00011;
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localparam READ_MEM = 5'b00100;
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localparam READ_MEM = 5'b00100;
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localparam DUMMY_WRT_CALC = 5'b00101;
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localparam DUMMY_WRT_CALC = 5'b00101;
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localparam WRITE_MEM = 5'b00110;
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localparam WRITE_MEM = 5'b00110;
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| Line 100... |
Line 100... |
localparam RESET = 5'b11111;
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localparam RESET = 5'b11111;
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// OPCODES TODO: verify how this get synthesised
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// OPCODES TODO: verify how this get synthesised
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`include "T6507LP_Package.v"
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`include "T6507LP_Package.v"
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// control signals
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// mem_rw signals
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localparam MEM_READ = 1'b0;
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localparam MEM_READ = 1'b0;
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localparam MEM_WRITE = 1'b1;
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localparam MEM_WRITE = 1'b1;
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reg [ADDR_SIZE_:0] pc; // program counter
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reg [ADDR_SIZE_:0] pc; // program counter
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reg [DATA_SIZE:0] sp; // stack pointer. 9 bits wide.
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reg [DATA_SIZE:0] sp; // stack pointer. 9 bits wide.
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| Line 205... |
Line 205... |
temp_addr <= 13'h0000;
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temp_addr <= 13'h0000;
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temp_data <= 8'h00;
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temp_data <= 8'h00;
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state <= RESET;
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state <= RESET;
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// registered outputs also receive default values
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// registered outputs also receive default values
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address <= 0;
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address <= 0;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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else begin
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else begin
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state <= next_state;
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state <= next_state;
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| Line 223... |
Line 223... |
FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)
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FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)
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*/
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*/
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FETCH_OP, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
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FETCH_OP, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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ir <= data_in;
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ir <= data_in;
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end
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end
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/*
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/*
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in this state the opcode is already known so truly execution begins.
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in this state the opcode is already known so truly execution begins.
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all instruction execute this cycle.
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all instruction execute this cycle.
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*/
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*/
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FETCH_LOW: begin
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FETCH_LOW: begin
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if (accumulator || implied) begin
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if (accumulator || implied) begin
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pc <= pc; // is this better?
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pc <= pc; // is this better?
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address <= pc;
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address <= pc;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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end
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end
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else if (immediate || relative) begin
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else if (immediate || relative) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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temp_data <= data_in; // the follow-up byte is saved in temp_data
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temp_data <= data_in; // the follow-up byte is saved in temp_data
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end
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end
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else if (absolute || absolute_indexed || jump_indirect) begin
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else if (absolute || absolute_indexed || jump_indirect) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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temp_addr <= {{5{1'b0}},data_in};
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temp_addr <= {{5{1'b0}},data_in};
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temp_data <= 8'h00;
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temp_data <= 8'h00;
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end
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end
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else if (zero_page) begin
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else if (zero_page) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= {{5{1'b0}},data_in};
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address <= {{5{1'b0}},data_in};
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temp_addr <= {{5{1'b0}},data_in};
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temp_addr <= {{5{1'b0}},data_in};
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if (write) begin
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if (write) begin
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control <= MEM_WRITE;
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mem_rw <= MEM_WRITE;
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data_out <= alu_result;
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data_out <= alu_result;
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end
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end
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else begin
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else begin
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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end
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end
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else if (zero_page_indexed) begin
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else if (zero_page_indexed) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= {{5{1'b0}}, data_in};
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address <= {{5{1'b0}}, data_in};
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temp_addr <= {{5{1'b0}}, data_in};
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temp_addr <= {{5{1'b0}}, data_in};
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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end
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end
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else if (indirectx || indirecty) begin
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else if (indirectx || indirecty) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= data_in;
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address <= data_in;
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temp_data <= data_in;
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temp_data <= data_in;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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end
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end
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else begin // the special instructions will fall here: BRK, RTI, RTS...
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else begin // the special instructions will fall here: BRK, RTI, RTS...
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if (brk) begin
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if (brk) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= sp;
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address <= sp;
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data_out <= {{3{1'b0}}, pc[12:8]};
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data_out <= {{3{1'b0}}, pc[12:8]};
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control <= MEM_WRITE;
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mem_rw <= MEM_WRITE;
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end
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end
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else if (rti || rts) begin
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else if (rti || rts) begin
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address <= sp;
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address <= sp;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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end
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end
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else if (pha || php) begin
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else if (pha || php) begin
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pc <= pc;
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pc <= pc;
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address <= sp;
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address <= sp;
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data_out <= (pha) ? alu_result : alu_status;
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data_out <= (pha) ? alu_result : alu_status;
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control <= MEM_WRITE;
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mem_rw <= MEM_WRITE;
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end
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end
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else if (pla || plp) begin
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else if (pla || plp) begin
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pc <= pc;
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pc <= pc;
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address <= sp;
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address <= sp;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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end
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end
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else begin // jsr
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else begin // jsr
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address <= sp;
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address <= sp;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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temp_addr <= {{5{1'b0}}, data_in};
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temp_addr <= {{5{1'b0}}, data_in};
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pc <= next_pc;
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pc <= next_pc;
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end
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end
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end
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end
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end
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end
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FETCH_HIGH_CALC_INDEX: begin
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FETCH_HIGH_CALC_INDEX: begin
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pc <= next_pc;
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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temp_addr[12:8] <= data_in[4:0];
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address <= {data_in[4:0], address_plus_index[7:0]};
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address <= {data_in[4:0], address_plus_index[7:0]};
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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// this cycle fetchs the next operand while still evaluating if a branch occurred.
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// this cycle fetchs the next operand while still evaluating if a branch occurred.
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FETCH_OP_EVAL_BRANCH: begin
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FETCH_OP_EVAL_BRANCH: begin
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if (branch) begin
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if (branch) begin
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pc <= {{5{1'b0}}, address_plus_index[7:0]};
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pc <= {{5{1'b0}}, address_plus_index[7:0]};
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address <= {{5{1'b0}}, address_plus_index[7:0]};
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address <= {{5{1'b0}}, address_plus_index[7:0]};
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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else begin
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else begin
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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ir <= data_in;
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ir <= data_in;
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end
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end
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end
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end
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// sometimes when reading memory page crosses may occur. the pc register must be fixed, i.e., add 16'h0100
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// sometimes when reading memory page crosses may occur. the pc register must be fixed, i.e., add 16'h0100
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| Line 337... |
Line 337... |
address[12:8] <= address_plus_index[12:8];
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address[12:8] <= address_plus_index[12:8];
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end
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end
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else begin
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else begin
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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ir <= data_in;
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ir <= data_in;
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end
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end
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end
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end
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// several instructions ocupy 3 bytes in memory. this cycle reads the third byte.
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// several instructions ocupy 3 bytes in memory. this cycle reads the third byte.
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FETCH_HIGH: begin
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FETCH_HIGH: begin
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if (jump) begin
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if (jump) begin
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pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
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pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
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address <= {data_in[4:0], temp_addr[7:0]};
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address <= {data_in[4:0], temp_addr[7:0]};
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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else begin
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else begin
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if (write) begin
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if (write) begin
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pc <= next_pc;
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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temp_addr[12:8] <= data_in[4:0];
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address <= {data_in[4:0],temp_addr[7:0]};
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address <= {data_in[4:0],temp_addr[7:0]};
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control <= MEM_WRITE;
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mem_rw <= MEM_WRITE;
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data_out <= alu_result;
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data_out <= alu_result;
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end
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end
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else begin // read_modify_write or just read
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else begin // read_modify_write or just read
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pc <= next_pc;
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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temp_addr[12:8] <= data_in[4:0];
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address <= {data_in[4:0],temp_addr[7:0]};
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address <= {data_in[4:0],temp_addr[7:0]};
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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end
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end
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end
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end
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READ_MEM: begin
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READ_MEM: begin
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if (read_modify_write) begin
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if (read_modify_write) begin
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pc <= pc;
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pc <= pc;
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address <= temp_addr;
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address <= temp_addr;
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control <= MEM_WRITE;
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mem_rw <= MEM_WRITE;
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temp_data <= data_in;
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temp_data <= data_in;
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data_out <= data_in; // writeback the same value
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data_out <= data_in; // writeback the same value
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end
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end
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else begin
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else begin
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pc <= pc;
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pc <= pc;
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address <= pc;
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address <= pc;
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temp_data <= data_in;
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temp_data <= data_in;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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end
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end
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READ_MEM_CALC_INDEX: begin
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READ_MEM_CALC_INDEX: begin
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address <= address_plus_index;
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address <= address_plus_index;
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temp_addr <= address_plus_index;
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temp_addr <= address_plus_index;
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if (write) begin
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if (write) begin
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control <= MEM_WRITE;
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mem_rw <= MEM_WRITE;
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data_out <= alu_result;
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data_out <= alu_result;
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end
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end
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else begin
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else begin
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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end
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end
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READ_MEM_FIX_ADDR: begin
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READ_MEM_FIX_ADDR: begin
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if (read) begin
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if (read) begin
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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if (page_crossed) begin
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if (page_crossed) begin
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address <= address_plus_index;
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address <= address_plus_index;
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temp_addr <= address_plus_index;
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temp_addr <= address_plus_index;
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| Line 411... |
Line 411... |
address <= pc;
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address <= pc;
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temp_data <= data_in;
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temp_data <= data_in;
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end
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end
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end
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end
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else if (write) begin
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else if (write) begin
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control <= MEM_WRITE;
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mem_rw <= MEM_WRITE;
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data_out <= alu_result;
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data_out <= alu_result;
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address <= address_plus_index;
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address <= address_plus_index;
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temp_addr <= address_plus_index;
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temp_addr <= address_plus_index;
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end
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end
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else begin // read modify write
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else begin // read modify write
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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address <= address_plus_index;
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address <= address_plus_index;
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temp_addr <= address_plus_index;
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temp_addr <= address_plus_index;
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end
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end
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end
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end
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DUMMY_WRT_CALC: begin
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DUMMY_WRT_CALC: begin
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pc <= pc;
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pc <= pc;
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address <= temp_addr;
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address <= temp_addr;
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control <= MEM_WRITE;
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mem_rw <= MEM_WRITE;
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data_out <= alu_result;
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data_out <= alu_result;
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end
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end
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WRITE_MEM: begin
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WRITE_MEM: begin
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pc <= pc;
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pc <= pc;
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address <= pc;
|
address <= pc;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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READ_FROM_POINTER: begin
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READ_FROM_POINTER: begin
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if (jump_indirect) begin
|
if (jump_indirect) begin
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pc[7:0] <= data_in;
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pc[7:0] <= data_in;
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control <= MEM_READ;
|
mem_rw <= MEM_READ;
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address <= address_plus_index;
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address <= address_plus_index;
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end
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end
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else begin
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else begin
|
pc <= pc;
|
pc <= pc;
|
control <= MEM_READ;
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mem_rw <= MEM_READ;
|
|
|
if (indirectx) begin
|
if (indirectx) begin
|
address <= address_plus_index;
|
address <= address_plus_index;
|
end
|
end
|
else begin // indirecty falls here
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else begin // indirecty falls here
|
| Line 459... |
Line 459... |
end
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end
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READ_FROM_POINTER_X: begin
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READ_FROM_POINTER_X: begin
|
pc <= pc;
|
pc <= pc;
|
address <= address_plus_index;
|
address <= address_plus_index;
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temp_addr[7:0] <= data_in;
|
temp_addr[7:0] <= data_in;
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control <= MEM_READ;
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mem_rw <= MEM_READ;
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end
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end
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READ_FROM_POINTER_X1: begin
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READ_FROM_POINTER_X1: begin
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if (jump_indirect) begin
|
if (jump_indirect) begin
|
pc[12:8] <= data_in[4:0];
|
pc[12:8] <= data_in[4:0];
|
control <= MEM_READ;
|
mem_rw <= MEM_READ;
|
address <= {data_in[4:0], pc[7:0]};
|
address <= {data_in[4:0], pc[7:0]};
|
end
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end
|
else if (indirectx) begin
|
else if (indirectx) begin
|
address <= {data_in[4:0], temp_addr[7:0]};
|
address <= {data_in[4:0], temp_addr[7:0]};
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if (write) begin
|
if (write) begin
|
control <= MEM_WRITE;
|
mem_rw <= MEM_WRITE;
|
data_out <= alu_result;
|
data_out <= alu_result;
|
end
|
end
|
else begin
|
else begin
|
control <= MEM_READ;
|
mem_rw <= MEM_READ;
|
end
|
end
|
end
|
end
|
else begin // indirecty falls here
|
else begin // indirecty falls here
|
address <= address_plus_index;
|
address <= address_plus_index;
|
temp_addr[12:8] <= data_in;
|
temp_addr[12:8] <= data_in;
|
control <= MEM_READ;
|
mem_rw <= MEM_READ;
|
end
|
end
|
end
|
end
|
PUSH_PCH: begin
|
PUSH_PCH: begin
|
pc <= pc;
|
pc <= pc;
|
address <= sp_minus_one;
|
address <= sp_minus_one;
|
data_out <= pc[7:0];
|
data_out <= pc[7:0];
|
control <= MEM_WRITE;
|
mem_rw <= MEM_WRITE;
|
sp <= sp_minus_one;
|
sp <= sp_minus_one;
|
end
|
end
|
PUSH_PCL: begin
|
PUSH_PCL: begin
|
if (jsr) begin
|
if (jsr) begin
|
pc <= pc;
|
pc <= pc;
|
address <= pc;
|
address <= pc;
|
control <= MEM_READ;
|
mem_rw <= MEM_READ;
|
sp <= sp_minus_one;
|
sp <= sp_minus_one;
|
end
|
end
|
else begin
|
else begin
|
pc <= pc;
|
pc <= pc;
|
address <= sp_minus_one;
|
address <= sp_minus_one;
|
data_out <= alu_status;
|
data_out <= alu_status;
|
control <= MEM_WRITE;
|
mem_rw <= MEM_WRITE;
|
sp <= sp_minus_one;
|
sp <= sp_minus_one;
|
end
|
end
|
end
|
end
|
PUSH_STATUS: begin
|
PUSH_STATUS: begin
|
address <= 13'hFFFE;
|
address <= 13'hFFFE;
|
control <= MEM_READ;
|
mem_rw <= MEM_READ;
|
end
|
end
|
FETCH_PCL: begin
|
FETCH_PCL: begin
|
pc[7:0] <= data_in;
|
pc[7:0] <= data_in;
|
address <= 13'hFFFF;
|
address <= 13'hFFFF;
|
control <= MEM_READ;
|
mem_rw <= MEM_READ;
|
end
|
end
|
FETCH_PCH: begin
|
FETCH_PCH: begin
|
pc[12:8] <= data_in[4:0];
|
pc[12:8] <= data_in[4:0];
|
address <= {data_in[4:0], pc[7:0]};
|
address <= {data_in[4:0], pc[7:0]};
|
control <= MEM_READ;
|
mem_rw <= MEM_READ;
|
end
|
end
|
INCREMENT_SP: begin
|
INCREMENT_SP: begin
|
sp <= sp_plus_one;
|
sp <= sp_plus_one;
|
address <= sp_plus_one;
|
address <= sp_plus_one;
|
end
|
end
|
| Line 545... |
Line 545... |
end
|
end
|
PUSH_REGISTER: begin
|
PUSH_REGISTER: begin
|
pc <= pc;
|
pc <= pc;
|
address <= pc;
|
address <= pc;
|
sp <= sp_minus_one;
|
sp <= sp_minus_one;
|
control <= MEM_READ;
|
mem_rw <= MEM_READ;
|
temp_data <= data_in;
|
temp_data <= data_in;
|
end
|
end
|
PULL_REGISTER: begin
|
PULL_REGISTER: begin
|
pc <= pc;
|
pc <= pc;
|
address <= pc;
|
address <= pc;
|
temp_data <= data_in;
|
temp_data <= data_in;
|
end
|
end
|
DUMMY: begin
|
DUMMY: begin
|
address <= sp;
|
address <= sp;
|
control <= MEM_WRITE;
|
mem_rw <= MEM_WRITE;
|
end
|
end
|
default: begin
|
default: begin
|
$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
|
$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
|
$finish(0);
|
$finish(0);
|
end
|
end
|
