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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Diff between revs 115 and 117

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////                                                                    ////
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////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
 
 
`include "timescale.v"
`include "timescale.v"
 
 
module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, mem_rw, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, alu_x, alu_y, address, mem_rw, data_out, alu_opcode, alu_a, alu_enable);
        parameter [3:0] DATA_SIZE = 4'd8;
        parameter [3:0] DATA_SIZE = 4'd8;
        parameter [3:0] ADDR_SIZE = 4'd13;
        parameter [3:0] ADDR_SIZE = 4'd13;
 
 
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
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        input clk;                              // master clock
        input clk;                              // master clock
        input reset_n;                          // active low reset
        input reset_n;                          // active low reset
        input [DATA_SIZE_:0] alu_result; // result from alu operation
        input [DATA_SIZE_:0] alu_result; // result from alu operation
        input [DATA_SIZE_:0] alu_status; // alu status register
        input [DATA_SIZE_:0] alu_status; // alu status register
        input [DATA_SIZE_:0] data_in;            // data that comes from the bus controller
        input [DATA_SIZE_:0] data_in;            // data that comes from the bus controller
 
        input [DATA_SIZE_:0] alu_x;              // alu x index register
 
        input [DATA_SIZE_:0] alu_y;              // alu y index register
        output reg [ADDR_SIZE_:0] address;       // system bus address
        output reg [ADDR_SIZE_:0] address;       // system bus address
        output reg mem_rw;                      // read = 0, write = 1
        output reg mem_rw;                      // read = 0, write = 1
        output reg [DATA_SIZE_:0] data_out;      // data that will be written somewhere else
        output reg [DATA_SIZE_:0] data_out;      // data that will be written somewhere else
        output reg [DATA_SIZE_:0] alu_opcode;    // current opcode
        output reg [DATA_SIZE_:0] alu_opcode;    // current opcode
        output reg [DATA_SIZE_:0] alu_a; // extra operand sent to the alu
        output reg [DATA_SIZE_:0] alu_a; // extra operand sent to the alu
        output reg alu_enable;                  // a flag that when high tells the alu when to perform the operations
        output reg alu_enable;                  // a flag that when high tells the alu when to perform the operations
 
 
        input [DATA_SIZE_:0] alu_x;
 
        input [DATA_SIZE_:0] alu_y;
 
 
 
        // FSM states. If aiming for less power consumption try gray coding.
        // FSM states. If aiming for less power consumption try gray coding.
        //localparam FETCH_OP_CALC = 5'b00001; this was never used
        //localparam FETCH_OP_CALC = 5'b00001; this was never used
        localparam FETCH_OP = 5'b00000;
        localparam FETCH_OP = 5'b00000;
        localparam FETCH_LOW = 5'b00010;
        localparam FETCH_LOW = 5'b00010;

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