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//// Description ////
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//// Description ////
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//// 6507 FSM ////
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//// 6507 FSM ////
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//// ////
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//// ////
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//// TODO: ////
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//// TODO: ////
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//// - Fix relative mode, bit 7 means negative ////
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//// - Fix relative mode, bit 7 means negative ////
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//// - Check reset behavior ////
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//// - Comment the code ////
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//// - Comment the code ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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| Line 142... |
Line 143... |
reg php;
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reg php;
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reg pla;
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reg pla;
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reg plp;
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reg plp;
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reg jsr;
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reg jsr;
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wire [ADDR_SIZE_:0] next_pc;
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wire [ADDR_SIZE_:0] next_pc; // a simple logic to add one to the PC
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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wire [8:0] sp_plus_one; // simple adder and subtracter for the stack pointer
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reg page_crossed; // so the simple assign was changed into a combinational always block
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assign sp_plus_one = sp + 9'b000000001;
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wire [8:0] sp_minus_one;
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assign sp_minus_one = sp - 9'b000000001;
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reg [ADDR_SIZE_:0] address_plus_index; // this two registers are used when the instruction uses indexing.
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reg page_crossed; // address_plus_index always adds index to address and page_crossed asserts when the sum creates a carry.
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reg branch;
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reg branch; // a simple reg that is asserted everytime a branch will be executed.
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// this is the combinational logic related to indexed instructions
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always @(*) begin
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always @(*) begin
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address_plus_index = 8'h00;
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address_plus_index = 8'h00;
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page_crossed = 1'b0;
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page_crossed = 1'b0;
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if (state == READ_MEM_CALC_INDEX || state == READ_MEM_FIX_ADDR || state == FETCH_HIGH_CALC_INDEX) begin
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if (state == READ_MEM_CALC_INDEX || state == READ_MEM_FIX_ADDR || state == FETCH_HIGH_CALC_INDEX) begin
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| Line 188... |
Line 196... |
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
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{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
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address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
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address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
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end
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end
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end
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end
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wire [8:0] sp_plus_one;
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assign sp_plus_one = sp + 9'b000000001;
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wire [8:0] sp_minus_one;
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assign sp_minus_one = sp - 9'b000000001;
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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// all registers must assume default values
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// all registers must assume default values
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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sp <= 9'b000000000; // the default is 'h100
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sp <= 9'b000000000; // the default is 'h100
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ir <= 8'h00;
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ir <= 8'h00;
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temp_addr <= 13'h0000;
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temp_addr <= 13'h0000;
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temp_data <= 8'h00;
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temp_data <= 8'h00;
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state <= RESET;
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state <= RESET;
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// registered outputs also receive default values
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// registered outputs also receive default values
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address <= 0;
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address <= 13'h0000;
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mem_rw <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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else begin
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else begin
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state <= next_state;
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state <= next_state;
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Line 230... |
mem_rw <= MEM_READ;
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mem_rw <= MEM_READ;
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ir <= data_in;
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ir <= data_in;
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end
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end
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/*
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/*
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in this state the opcode is already known so truly execution begins.
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in this state the opcode is already known so truly execution begins.
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all instruction execute this cycle.
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all instructions execute this cycle.
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*/
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*/
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FETCH_LOW: begin
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FETCH_LOW: begin
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if (accumulator || implied) begin
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if (accumulator || implied) begin
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pc <= pc; // is this better?
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pc <= pc; // is this better?
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address <= pc;
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address <= pc;
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Line 368... |
mem_rw <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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end
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end
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end
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end
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// read memory at address
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READ_MEM: begin
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READ_MEM: begin
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if (read_modify_write) begin
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if (read_modify_write) begin
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pc <= pc;
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pc <= pc;
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address <= temp_addr;
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address <= temp_addr;
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mem_rw <= MEM_WRITE;
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mem_rw <= MEM_WRITE;
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Line 404... |
READ_MEM_FIX_ADDR: begin
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READ_MEM_FIX_ADDR: begin
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if (read) begin
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if (read) begin
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mem_rw <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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if (page_crossed) begin
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if (page_crossed) begin // fix address
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address <= address_plus_index;
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address <= address_plus_index;
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temp_addr <= address_plus_index;
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temp_addr <= address_plus_index;
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end
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end
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else begin
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else begin
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address <= pc;
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address <= pc;
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Line 427... |
data_out <= 8'h00;
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data_out <= 8'h00;
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address <= address_plus_index;
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address <= address_plus_index;
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temp_addr <= address_plus_index;
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temp_addr <= address_plus_index;
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end
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end
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end
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end
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// some instructions have a dummy write cycle. this is it.
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DUMMY_WRT_CALC: begin
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DUMMY_WRT_CALC: begin
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pc <= pc;
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pc <= pc;
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address <= temp_addr;
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address <= temp_addr;
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mem_rw <= MEM_WRITE;
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mem_rw <= MEM_WRITE;
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data_out <= alu_result;
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data_out <= alu_result;
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Line 570... |
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endcase
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endcase
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end
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end
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end
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end
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always @ (*) begin // this is the next_state logic and the output logic always block
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always @ (*) begin // this is the next_state logic and the combinational output logic always block
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alu_opcode = 8'h00;
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alu_opcode = 8'h00;
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alu_a = 8'h00;
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alu_a = 8'h00;
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alu_enable = 1'b0;
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alu_enable = 1'b0;
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next_state = RESET; // these lines prevents latches
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next_state = RESET; // these lines prevents latches
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