| Line 142... |
Line 142... |
reg pha;
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reg pha;
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reg php;
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reg php;
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reg pla;
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reg pla;
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reg plp;
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reg plp;
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reg jsr;
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reg jsr;
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reg tsx;
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reg txs;
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|
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wire [ADDR_SIZE_:0] next_pc; // a simple logic to add one to the PC
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wire [ADDR_SIZE_:0] next_pc; // a simple logic to add one to the PC
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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|
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wire [8:0] sp_plus_one; // simple adder and subtracter for the stack pointer
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wire [8:0] sp_plus_one; // simple adder and subtracter for the stack pointer
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| Line 202... |
Line 204... |
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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// all registers must assume default values
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// all registers must assume default values
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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sp <= 9'b000000000; // the default is 'h100
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sp <= 9'b111111111; // the default is 'h1FF
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ir <= 8'h00;
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ir <= 8'h00;
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temp_addr <= 13'h0000;
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temp_addr <= 13'h0000;
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temp_data <= 8'h00;
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temp_data <= 8'h00;
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state <= RESET;
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state <= RESET;
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// registered outputs also receive default values
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// registered outputs also receive default values
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| Line 219... |
Line 221... |
state <= next_state;
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state <= next_state;
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|
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case (state)
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case (state)
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RESET: begin // The processor was reset
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RESET: begin // The processor was reset
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rst_counter <= rst_counter + 1;
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rst_counter <= rst_counter + 1;
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sp <= 9'b100000000; // this prevents flipflops with different drivers
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//sp <= 9'b111111111; // this prevents flipflops with different drivers
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//$write("under reset");
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//$write("under reset");
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end
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end
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/*
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/*
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FETCH_OP: executed when the processor was reset or the last instruction could not fetch.
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FETCH_OP: executed when the processor was reset or the last instruction could not fetch.
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FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)
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FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)
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| Line 241... |
Line 243... |
FETCH_LOW: begin
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FETCH_LOW: begin
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if (accumulator || implied) begin
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if (accumulator || implied) begin
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pc <= pc; // is this better?
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pc <= pc; // is this better?
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address <= pc;
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address <= pc;
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mem_rw <= MEM_READ;
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mem_rw <= MEM_READ;
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|
|
|
if (txs) begin
|
|
sp[7:0] <= data_in;
|
|
end
|
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//alu_a
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end
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end
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else if (immediate || relative) begin
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else if (immediate || relative) begin
|
pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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mem_rw <= MEM_READ;
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mem_rw <= MEM_READ;
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| Line 600... |
Line 607... |
FETCH_LOW: begin
|
FETCH_LOW: begin
|
if (accumulator || implied) begin
|
if (accumulator || implied) begin
|
alu_opcode = ir;
|
alu_opcode = ir;
|
alu_enable = 1'b1;
|
alu_enable = 1'b1;
|
next_state = FETCH_OP;
|
next_state = FETCH_OP;
|
|
|
|
if (tsx) begin
|
|
alu_a = sp[7:0];
|
|
end
|
end
|
end
|
else if (immediate) begin
|
else if (immediate) begin
|
next_state = FETCH_OP_CALC_PARAM;
|
next_state = FETCH_OP_CALC_PARAM;
|
end
|
end
|
else if (zero_page) begin
|
else if (zero_page) begin
|
| Line 878... |
Line 889... |
pha = 1'b0;
|
pha = 1'b0;
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php = 1'b0;
|
php = 1'b0;
|
pla = 1'b0;
|
pla = 1'b0;
|
plp = 1'b0;
|
plp = 1'b0;
|
jsr = 1'b0;
|
jsr = 1'b0;
|
|
tsx = 1'b0;
|
|
txs = 1'b0;
|
|
|
case (ir)
|
case (ir)
|
CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP,
|
CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP,
|
SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
|
SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TXA_IMP, TYA_IMP: begin
|
implied = 1'b1;
|
implied = 1'b1;
|
end
|
end
|
ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
|
ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
|
accumulator = 1'b1;
|
accumulator = 1'b1;
|
end
|
end
|
| Line 1043... |
Line 1056... |
plp = 1'b1;
|
plp = 1'b1;
|
end
|
end
|
JSR_ABS: begin
|
JSR_ABS: begin
|
jsr = 1'b1;
|
jsr = 1'b1;
|
end
|
end
|
|
TSX_IMP: begin
|
|
tsx = 1'b1;
|
|
end
|
|
TXS_IMP: begin
|
|
txs = 1'b1;
|
|
end
|
default: begin
|
default: begin
|
//$write("state : %b", state);
|
//$write("state : %b", state);
|
if (reset_n == 1'b1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
|
if (reset_n == 1'b1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
|
//$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
|
//$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
|
//$finish();
|
//$finish();
|
