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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Diff between revs 195 and 196

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Rev 195 Rev 196
Line 245... Line 245...
                                                pc <= pc; // is this better?
                                                pc <= pc; // is this better?
                                                address <= pc;
                                                address <= pc;
                                                mem_rw <= MEM_READ;
                                                mem_rw <= MEM_READ;
 
 
                                                if (txs) begin
                                                if (txs) begin
                                                        sp[7:0] <= data_in;
                                                        sp[7:0] <= alu_x;
                                                end
                                                end
                                                //alu_a
                                                //alu_a
                                        end
                                        end
                                        else if (immediate || relative) begin
                                        else if (immediate || relative) begin
                                                pc <= next_pc;
                                                pc <= next_pc;
Line 523... Line 523...
                                        end
                                        end
                                end
                                end
                                PUSH_STATUS: begin
                                PUSH_STATUS: begin
                                        address <= 13'hFFFE;
                                        address <= 13'hFFFE;
                                        mem_rw <= MEM_READ;
                                        mem_rw <= MEM_READ;
 
                                        sp <= sp_minus_one;
                                end
                                end
                                FETCH_PCL: begin
                                FETCH_PCL: begin
                                        pc[7:0] <= data_in;
                                        pc[7:0] <= data_in;
                                        address <= 13'hFFFF;
                                        address <= 13'hFFFF;
                                        mem_rw <= MEM_READ;
                                        mem_rw <= MEM_READ;

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