| Line 148... |
Line 148... |
reg txs;
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reg txs;
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wire [ADDR_SIZE_:0] next_pc; // a simple logic to add one to the PC
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wire [ADDR_SIZE_:0] next_pc; // a simple logic to add one to the PC
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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wire [8:0] sp_plus_one; // simple adder and subtracter for the stack pointer
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wire [DATA_SIZE:0] sp_plus_one; // simple adder and subtracter for the stack pointer
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assign sp_plus_one = sp + 9'b000000001;
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assign sp_plus_one = {1'b1, sp[7:0] + 8'b000000001};
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wire [8:0] sp_minus_one;
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wire [DATA_SIZE:0] sp_minus_one;
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assign sp_minus_one = sp - 9'b000000001;
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assign sp_minus_one = {1'b1, sp[7:0] - 8'b000000001};
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reg [ADDR_SIZE_:0] address_plus_index; // this two registers are used when the instruction uses indexing.
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reg [ADDR_SIZE_:0] address_plus_index; // this two registers are used when the instruction uses indexing.
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reg page_crossed; // address_plus_index always adds index to address and page_crossed asserts when the sum creates a carry.
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reg page_crossed; // address_plus_index always adds index to address and page_crossed asserts when the sum creates a carry.
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reg branch; // a simple reg that is asserted everytime a branch will be executed.
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reg branch; // a simple reg that is asserted everytime a branch will be executed.
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// this is the combinational logic related to indexed instructions
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// this is the combinational logic related to indexed instructions
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always @(*) begin
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always @(*) begin
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address_plus_index = 8'h00;
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address_plus_index = 13'h000;
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page_crossed = 1'b0;
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page_crossed = 1'b0;
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if (state == READ_MEM_CALC_INDEX || state == READ_MEM_FIX_ADDR || state == FETCH_HIGH_CALC_INDEX) begin
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if ( (state == READ_MEM_CALC_INDEX) || (state == READ_MEM_FIX_ADDR) || (state == FETCH_HIGH_CALC_INDEX) ) begin
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{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
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{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
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address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
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address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
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end
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end
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else if (branch) begin
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else if (branch) begin
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if (state == FETCH_OP_FIX_PC || state == FETCH_OP_EVAL_BRANCH) begin
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if (state == FETCH_OP_FIX_PC || state == FETCH_OP_EVAL_BRANCH) begin
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| Line 180... |
Line 180... |
if (indirectx) begin
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if (indirectx) begin
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{page_crossed, address_plus_index[7:0]} = temp_data + index;
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{page_crossed, address_plus_index[7:0]} = temp_data + index;
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address_plus_index[12:8] = 5'b00000;
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address_plus_index[12:8] = 5'b00000;
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end
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end
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else if (jump_indirect) begin
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else if (jump_indirect) begin
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address_plus_index[7:0] = temp_addr[7:0] + 8'h01; // temp_addr should be 7:0?
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address_plus_index[7:0] = temp_addr[7:0] + 8'h01;
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address_plus_index[12:8] = 5'b00000;
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address_plus_index[12:8] = 5'b00000;
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end
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end
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else begin // indirecty falls here
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else begin // indirecty falls here
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address_plus_index[7:0] = temp_data + 8'h01;
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address_plus_index[7:0] = temp_data + 8'h01;
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address_plus_index[12:8] = 5'b00000;
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address_plus_index[12:8] = 5'b00000;
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| Line 203... |
Line 203... |
reg [2:0] rst_counter; // a counter to preserve the cpu idle for six cycles
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reg [2:0] rst_counter; // a counter to preserve the cpu idle for six cycles
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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// all registers must assume default values
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// all registers must assume default values
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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pc <= 13'h0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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sp <= 9'b111111111; // the default is 'h1FF
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sp <= 9'b111111111; // the default is 'h1FF
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ir <= 8'h00;
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ir <= 8'h00;
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temp_addr <= 13'h0000;
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temp_addr <= 13'h0000;
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temp_data <= 8'h00;
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temp_data <= 8'h00;
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state <= RESET;
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state <= RESET;
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// registered outputs also receive default values
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// registered outputs also receive default values
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address <= 13'h0000;
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address <= 13'h0000;
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mem_rw <= MEM_READ;
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mem_rw <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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rst_counter <= 0;
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rst_counter <= 3'h0;
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end
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end
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else begin
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else begin
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state <= next_state;
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state <= next_state;
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case (state)
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case (state)
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RESET: begin // The processor was reset
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RESET: begin // The processor was reset
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rst_counter <= rst_counter + 1;
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rst_counter <= rst_counter + 3'b001;
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//sp <= 9'b111111111; // this prevents flipflops with different drivers
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//sp <= 9'b111111111; // this prevents flipflops with different drivers
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//$write("under reset");
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//$write("under reset");
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end
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end
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/*
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/*
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FETCH_OP: executed when the processor was reset or the last instruction could not fetch.
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FETCH_OP: executed when the processor was reset or the last instruction could not fetch.
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| Line 590... |
Line 590... |
alu_enable = 1'b0;
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alu_enable = 1'b0;
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next_state = RESET; // these lines prevents latches
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next_state = RESET; // these lines prevents latches
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case (state)
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case (state)
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RESET: begin
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RESET: begin
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if (rst_counter == 6) begin
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if (rst_counter == 3'd6) begin
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next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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end
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end
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FETCH_OP: begin
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FETCH_OP: begin
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next_state = FETCH_LOW;
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next_state = FETCH_LOW;
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