Line 144... |
Line 144... |
reg pla;
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reg pla;
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reg plp;
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reg plp;
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reg jsr;
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reg jsr;
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reg tsx;
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reg tsx;
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reg txs;
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reg txs;
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reg nop;
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wire [ADDR_SIZE_:0] next_pc; // a simple logic to add one to the PC
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wire [ADDR_SIZE_:0] next_pc; // a simple logic to add one to the PC
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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wire [DATA_SIZE:0] sp_plus_one; // simple adder and subtracter for the stack pointer
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wire [DATA_SIZE:0] sp_plus_one; // simple adder and subtracter for the stack pointer
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Line 605... |
Line 606... |
alu_enable = 1'b1;
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alu_enable = 1'b1;
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alu_a = temp_data;
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alu_a = temp_data;
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end
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end
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FETCH_LOW: begin
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FETCH_LOW: begin
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if (accumulator || implied || txs) begin
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if (accumulator || implied || txs) begin
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if (!nop) begin
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alu_opcode = ir;
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alu_opcode = ir;
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alu_enable = 1'b1;
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alu_enable = 1'b1;
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end
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next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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else if (tsx) begin
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else if (tsx) begin
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alu_opcode = ir;
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alu_opcode = ir;
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alu_enable = 1'b1;
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alu_enable = 1'b1;
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Line 897... |
Line 900... |
pla = 1'b0;
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pla = 1'b0;
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plp = 1'b0;
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plp = 1'b0;
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jsr = 1'b0;
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jsr = 1'b0;
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tsx = 1'b0;
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tsx = 1'b0;
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txs = 1'b0;
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txs = 1'b0;
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nop = 1'b0;
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case (ir)
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case (ir)
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CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP,
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CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP,
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SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TXA_IMP, TYA_IMP: begin
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TAY_IMP, TXA_IMP, TYA_IMP: begin
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implied = 1'b1;
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end
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NOP_IMP: begin
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implied = 1'b1;
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implied = 1'b1;
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nop = 1'b1;
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end
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end
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ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
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ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
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accumulator = 1'b1;
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accumulator = 1'b1;
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end
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end
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ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
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ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
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