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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Diff between revs 202 and 205

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Rev 202 Rev 205
Line 144... Line 144...
        reg pla;
        reg pla;
        reg plp;
        reg plp;
        reg jsr;
        reg jsr;
        reg tsx;
        reg tsx;
        reg txs;
        reg txs;
 
        reg nop;
 
 
        wire [ADDR_SIZE_:0] next_pc;      // a simple logic to add one to the PC
        wire [ADDR_SIZE_:0] next_pc;      // a simple logic to add one to the PC
        assign next_pc = pc + 13'b0000000000001;
        assign next_pc = pc + 13'b0000000000001;
 
 
        wire [DATA_SIZE:0] sp_plus_one;          // simple adder and subtracter for the stack pointer
        wire [DATA_SIZE:0] sp_plus_one;          // simple adder and subtracter for the stack pointer
Line 605... Line 606...
                                alu_enable = 1'b1;
                                alu_enable = 1'b1;
                                alu_a = temp_data;
                                alu_a = temp_data;
                        end
                        end
                        FETCH_LOW: begin
                        FETCH_LOW: begin
                                if (accumulator  || implied || txs) begin
                                if (accumulator  || implied || txs) begin
 
                                        if (!nop) begin
                                        alu_opcode = ir;
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        alu_enable = 1'b1;
 
                                        end
                                        next_state = FETCH_OP;
                                        next_state = FETCH_OP;
                                end
                                end
                                else if (tsx) begin
                                else if (tsx) begin
                                        alu_opcode = ir;
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        alu_enable = 1'b1;
Line 897... Line 900...
                pla = 1'b0;
                pla = 1'b0;
                plp = 1'b0;
                plp = 1'b0;
                jsr = 1'b0;
                jsr = 1'b0;
                tsx = 1'b0;
                tsx = 1'b0;
                txs = 1'b0;
                txs = 1'b0;
 
                nop = 1'b0;
 
 
                case (ir)
                case (ir)
                        CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP,
                        CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP,
                        SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TXA_IMP, TYA_IMP: begin
                        TAY_IMP, TXA_IMP, TYA_IMP: begin
 
                                implied = 1'b1;
 
                        end
 
                        NOP_IMP: begin
                                implied = 1'b1;
                                implied = 1'b1;
 
                                nop = 1'b1;
                        end
                        end
                        ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
                        ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
                                accumulator = 1'b1;
                                accumulator = 1'b1;
                        end
                        end
                        ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
                        ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin

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