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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module t6507lp_fsm(clk_in, n_rst_in, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a);
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module t6507lp_fsm(clk_in, rst_in_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
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parameter DATA_SIZE = 4'd8;
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parameter ADDR_SIZE = 4'd13;
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input clk_in;
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input clk_in;
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input n_rst_in;
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input rst_in_n;
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input [7:0] alu_result;
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input [DATA_SIZE-1:0] alu_result;
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input [7:0] alu_status;
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input [DATA_SIZE-1:0] alu_status;
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input [7:0] data_in;
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input [DATA_SIZE-1:0] data_in;
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output reg [12:0] address;
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output reg [ADDR_SIZE-1:0] address;
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output reg control; // one bit is enough? read = 0, write = 1
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output reg control; // one bit is enough? read = 0, write = 1
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output reg [7:0] data_out;
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output reg [DATA_SIZE-1:0] data_out;
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output reg [7:0] alu_opcode;
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output reg [DATA_SIZE-1:0] alu_opcode;
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output reg [7:0] alu_a;
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output reg [DATA_SIZE-1:0] alu_a;
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output reg alu_enable;
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// FSM states
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// FSM states
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localparam RESET = 4'b1111;
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localparam FETCH_OP = 4'b0000;
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localparam FETCH_OP = 4'b0000;
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localparam FETCH_LOW = 4'b0001;
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localparam FETCH_OP_CALC = 4'b0001;
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localparam FETCH_HIGH = 4'b0010;
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localparam FETCH_LOW = 4'b0010;
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localparam SET_PC = 4'b0011;
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localparam FETCH_HIGH = 4'b0011;
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localparam READ_EFFECTIVE = 4'b0100;
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localparam DO_OPERATION = 4'b0101;
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localparam WRITE_DUMMY = 4'b0110;
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localparam WRITE_EFFECTIVE = 4'b0111;
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localparam CALCULATE_INDEX = 4'b1000;
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localparam CHECK_FOR_PAGE_CROSS = 4'b1001;
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// OPCODES TODO: verify how this get synthesised
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// OPCODES TODO: verify how this get synthesised
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`include "../T6507LP_Package.v"
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`include "../T6507LP_Package.v"
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// control signals
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// control signals
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localparam MEM_READ = 1'b0;
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localparam MEM_READ = 1'b0;
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localparam MEM_WRITE = 1'b1;
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localparam MEM_WRITE = 1'b1;
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reg [12:0] pc; // program counter
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reg [ADDR_SIZE-1:0] pc; // program counter
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reg [7:0] sp; // stack pointer
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reg [DATA_SIZE-1:0] sp; // stack pointer
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reg [7:0] ir; // instruction register
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reg [DATA_SIZE-1:0] ir; // instruction register
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reg [12:0] temp_add; // temporary address
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reg [ADDR_SIZE:0] temp_add; // temporary address
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reg [7:0] temp_data; // temporary data
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reg [DATA_SIZE-1:0] temp_data; // temporary data
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reg [3:0] state, next_state; // current and next state registers
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reg [3:0] state, next_state; // current and next state registers
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// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
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// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
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// wiring that simplifies the FSM logic
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// wiring that simplifies the FSM logic
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Line 104... |
reg read;
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reg read;
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reg read_modify_write;
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reg read_modify_write;
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reg write;
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reg write;
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reg jump;
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reg jump;
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reg enable;
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wire [ADDR_SIZE-1:0] next_pc;
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wire [12:0] next_pc;
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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always @ (posedge clk_in or negedge n_rst_in) begin
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always @ (posedge clk_in or negedge rst_in_n) begin
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if (n_rst_in == 1'b0) begin
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if (rst_in_n == 1'b0) begin
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// TODO: all registers must assume default values
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// TODO: all internal flip-flops must assume default values
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pc <= {13{1'b0}}; // TODO: this is written somewhere. something about a reset vector. must be checked.
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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sp <= 8'h00; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
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sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
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ir <= 8'h00;
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ir <= 0;
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temp_add <= {13{1'b0}};
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temp_add <= 0;
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temp_data <= {8{1'b0}};
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temp_data <= 0;
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state <= FETCH_OP;
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state <= RESET;
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//address <= {13{1'b0}};
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//control <= 1'b0;
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//data_out <= {8{1'b0}};
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//alu_opcode <= {8{1'b0}};
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//alu_a <= {8{1'b0}};
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end
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end
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else begin
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else begin
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state <= next_state;
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state <= next_state;
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address <= pc; // this secures the pipelining will happen by default
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case (state)
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case (state)
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RESET: begin
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// The processor was reset
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end
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FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
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FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
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// the last cycle was a memory write.
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// the last cycle was a memory write.
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pc <= next_pc;
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pc <= next_pc;
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end
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end
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FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
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FETCH_OP_CALC: begin // this is the pipeline happening!
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pc <= next_pc;
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ir <= data_in; // opcode must be saved in the instruction register. this is not necessary for the IMP and ACC modes.
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end
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FETCH_HIGH: begin
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pc <= next_pc;
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pc <= next_pc;
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temp_add <= {5'b00000, data_in}; // data from previous cycle (lowbyte) is ready and must be saved
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end
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SET_PC: begin
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pc <= {data_in[4:0], temp_add[7:0]};
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end
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READ_EFFECTIVE: begin
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if (zero_page) begin
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temp_add <= {5'b00000, data_in}; // this is necessary for the write_effective state
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address <= {5'b00000, data_in};
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end
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else if (zero_page_indexed) begin
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temp_add <= {5'b00000, alu_result}; // this is necessary for the write_effective state
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address <= {5'b00000, alu_result};
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end
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else begin
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temp_add[12:8] <= data_in;
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address <= {data_in[4:0], temp_add[7:0]};
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end
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end
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DO_OPERATION, CALCULATE_INDEX: begin
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end
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WRITE_DUMMY: begin
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//if (zero_page) begin // i believe this works fine
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address <= temp_add;
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//control <= WRITE; // just for compatibility
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//alu_opcode <= ir;
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//alu_a <= data_in;
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end
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end
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WRITE_EFFECTIVE: begin
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FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
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if (zero_page) begin
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if (accumulator || implied) begin
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address <= temp_add;
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pc <= pc; // is this necessary?
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end
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else if (zero_page_indexed) begin
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address <= {5'b00000, alu_result};
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end
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else begin // maybe this could be rearenged for better synth
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if (write) begin
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address <= {data_in[4:0], temp_add[7:0]};
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end
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end
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else begin
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else begin
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address <= temp_add;
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pc <= next_pc;
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end
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ir <= data_in; // opcode must be saved in the instruction register
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end
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//data_out <= alu_result;
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//control <= WRITE;
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end
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end
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CHECK_FOR_PAGE_CROSS: begin
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temp_add[12:8] <= data_in;
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address <= {data_in[4:0], temp_add[7:0]};
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end
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end
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default: begin
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default: begin
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state <= FETCH_OP; // TODO: this prevents the system from halting but may trigger strange behavior.
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$finish("UNKNOWN STATE!"); // TODO: check if synth really ignores this line. Otherwise wrap it with a `ifdef
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$finish(0);
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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always @(posedge clk_in) begin // combinational block that handles the outputs
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always @ (*) begin // this is the next_state logic and output logic always block
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enable <= 1'b0;
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address = pc;
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control <= MEM_READ;
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control = MEM_READ;
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alu_opcode <= 8'h00;
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data_out = 8'h00;
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alu_a <= 8'h00;
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alu_opcode = 8'h00;
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data_out <= 8'h00;
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alu_a = 8'h00;
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alu_enable = 1'b0;
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case (state)
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FETCH_OP, SET_PC, READ_EFFECTIVE: begin
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//enable = 0;
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end
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FETCH_LOW: begin
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if (accumulator || implied) begin // the ALU must be used
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enable <= 1'b1;
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alu_opcode <= data_in;
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end
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end
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FETCH_HIGH: begin
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if (immediate || write || absolute_indexed) begin
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enable <= 1'b1;
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alu_opcode <= ir;
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alu_a <= data_in;
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end
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end
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DO_OPERATION, CALCULATE_INDEX: begin
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enable <= 1'b1;
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alu_opcode <= ir;
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alu_a <= data_in;
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end
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WRITE_DUMMY: begin
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//if (zero_page) begin // i believe this works fine
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control <= MEM_WRITE; // just for compatibility
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data_out <= data_in; // just for compatibility
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alu_opcode <= ir;
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alu_a <= data_in;
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end
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WRITE_EFFECTIVE: begin
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control <= MEM_WRITE;
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data_out <= alu_result;
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end
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endcase
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end
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always @ (*) begin // this is the next_state always
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next_state = FETCH_OP; // this should avoid latch inferring
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next_state = RESET; // this prevents the latch
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begin
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begin
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case (state)
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case (state)
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FETCH_OP: begin
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RESET: begin
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next_state = FETCH_LOW;
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next_state = FETCH_OP;
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end
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FETCH_LOW: begin
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if (accumulator || implied) begin
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next_state = FETCH_OP; // not sure
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end
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else if (zero_page) begin // zero page behaves exactly as absolute except that it has only the first fetch
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if (read || read_modify_write) begin
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next_state = READ_EFFECTIVE;
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end
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else if (write) begin
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next_state = WRITE_EFFECTIVE;
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end
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end
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else if (zero_page_indexed) begin
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next_state = CALCULATE_INDEX;
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end
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else begin
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next_state = FETCH_HIGH;
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end
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end
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end
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FETCH_HIGH: begin
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FETCH_OP: begin
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if (immediate) begin
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next_state = FETCH_LOW;
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next_state = FETCH_LOW;
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end
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end
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else if (absolute) begin
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FETCH_OP_CALC: begin
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if (jump) begin
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next_state = SET_PC;
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end
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else if (read || read_modify_write) begin // TODO: verify if this should stay like this
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// (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, LAX, NOP) reads
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// (ASL, LSR, ROL, ROR, INC, DEC, SLO, SRE, RLA, RRA, ISB, DCP) modifs
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// (STA, STX, STY, SAX) writes
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next_state = READ_EFFECTIVE;
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end
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else if (write) begin
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next_state = WRITE_EFFECTIVE;
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end
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end
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else if (absolute_indexed) begin
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next_state = CHECK_FOR_PAGE_CROSS;
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end
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end
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SET_PC, DO_OPERATION: begin
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next_state = FETCH_LOW;
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next_state = FETCH_LOW;
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alu_opcode = ir;
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alu_enable = 1'b1;
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end
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end
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READ_EFFECTIVE: begin
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FETCH_LOW: begin
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if (read) begin
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if (accumulator || implied) begin
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next_state = DO_OPERATION;
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alu_opcode = data_in;
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end
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alu_enable = 1'b1;
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else if (read_modify_write) begin
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next_state = WRITE_DUMMY;
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end
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end
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WRITE_EFFECTIVE: begin
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next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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CALCULATE_INDEX: begin
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else if (immediate) begin
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if (read || read_modify_write) begin
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next_state = FETCH_OP_CALC;
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next_state = READ_EFFECTIVE;
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end
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else if (write) begin
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next_state = WRITE_EFFECTIVE;
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end
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end
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CHECK_FOR_PAGE_CROSS: begin
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if (alu_status[V] == 1'b0) begin // check the overflow bit
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if (read || read_modify_write) begin
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next_state = READ_EFFECTIVE;
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end
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else begin
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next_state = WRITE_EFFECTIVE;
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end
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end
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else begin // TODO: this is totally uncertain. absolute indexed mode must be reviewed
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if (read || read_modify_write) begin
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next_state = DO_OPERATION;
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end
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end
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else begin
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else begin // at least the immediate address mode falls here
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next_state = WRITE_EFFECTIVE;
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next_state = FETCH_HIGH;
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end
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end
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end
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end
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default: begin
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next_state = RESET;
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end
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end
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//end
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endcase
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endcase
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end
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end
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end
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end
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// this always block is responsible for updating the address mode
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// this always block is responsible for updating the address mode
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always @ (*) begin // TODO: the sensitivity may not be correct
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always @ (*) begin //
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absolute = 1'b0;
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absolute = 1'b0;
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absolute_indexed = 1'b0;
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absolute_indexed = 1'b0;
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accumulator = 1'b0;
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accumulator = 1'b0;
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immediate = 1'b0;
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immediate = 1'b0;
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implied = 1'b0;
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implied = 1'b0;
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| Line 361... |
Line 210... |
read = 1'b0;
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read = 1'b0;
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read_modify_write = 1'b0;
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read_modify_write = 1'b0;
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write = 1'b0;
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write = 1'b0;
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jump = 1'b0;
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jump = 1'b0;
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if (state == FETCH_LOW) begin // TODO: does this works?
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if (state == FETCH_LOW) begin
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case (data_in)
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case (data_in)
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BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
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BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
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PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
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PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
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implied = 1'b1;
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implied = 1'b1;
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end
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end
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