| Line 107... |
Line 107... |
reg jump;
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reg jump;
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wire [ADDR_SIZE-1:0] next_pc;
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wire [ADDR_SIZE-1:0] next_pc;
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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|
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always @ (posedge clk_in or negedge rst_in_n) begin
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always @ (posedge clk_in or negedge rst_in_n) begin // sequencial always block
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if (rst_in_n == 1'b0) begin
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if (rst_in_n == 1'b0) begin
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// TODO: all internal flip-flops must assume default values
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// TODO: all internal flip-flops must assume default values
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|
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
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sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
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| Line 128... |
Line 128... |
// The processor was reset
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// The processor was reset
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end
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end
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FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
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FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
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// the last cycle was a memory write.
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// the last cycle was a memory write.
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pc <= next_pc;
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pc <= next_pc;
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ir <= data_in;
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end
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end
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FETCH_OP_CALC: begin // this is the pipeline happening!
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FETCH_OP_CALC: begin // this is the pipeline happening!
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pc <= next_pc;
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pc <= next_pc;
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ir <= data_in;
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end
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end
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FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
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FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
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if (accumulator || implied) begin
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if (accumulator || implied) begin
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pc <= pc; // is this necessary?
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pc <= pc; // is this better?
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end
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end
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else begin
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else if (immediate) begin
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pc <= next_pc;
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pc <= next_pc;
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ir <= data_in; // opcode must be saved in the instruction register
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temp_data <= data_in; // the follow-up byte is saved in temp_data
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end
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end
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default: begin
|
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
|
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$finish(0);
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end
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|
|
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endcase
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end
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end
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|
|
|
always @ (posedge clk_in or negedge rst_in_n) begin
|
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if (rst_in_n == 1'b0) begin
|
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// TODO: all outputs must assume default values
|
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address <= 0;
|
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control <= 0; // one bit is enough? read = 0, write = 1
|
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data_out <= 0;
|
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alu_opcode <= 0;
|
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alu_a <= 0;
|
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alu_enable <= 0;
|
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end
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else begin
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|
|
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address <= pc;
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|
|
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case (state)
|
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RESET: begin
|
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// The processor was reset. No output whatsoever.
|
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end
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FETCH_OP: begin
|
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// it is a simple fetch. no output change.
|
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end
|
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FETCH_OP_CALC: begin // this is the pipeline happening!
|
|
alu_opcode <= ir;
|
|
alu_a <= temp_data;
|
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alu_enable <= 1'b1;
|
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end
|
|
FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
|
|
if (accumulator || implied) begin
|
|
alu_opcode <= ir;
|
|
alu_enable <= 1'b1;
|
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end
|
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else begin // nothing?
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|
|
end
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end
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end
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end
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default: begin
|
default: begin
|
$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
|
$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
|
$finish(0);
|
$finish(0);
|
end
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end
|
|
|
endcase
|
endcase
|
end
|
end
|
|
|
end
|
end
|
|
|
always @ (*) begin // this is the next_state logic and output logic always block
|
always @ (*) begin // this is the next_state logic always block
|
address = pc;
|
//address = pc;
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control = MEM_READ;
|
//control = MEM_READ;
|
data_out = 8'h00;
|
//data_out = 8'h00;
|
alu_opcode = 8'h00;
|
//alu_opcode = 8'h00;
|
alu_a = 8'h00;
|
//alu_a = 8'h00;
|
alu_enable = 1'b0;
|
//alu_enable = 1'b0;
|
|
|
next_state = RESET; // this prevents the latch
|
next_state = RESET; // this prevents the latch
|
|
|
begin
|
begin
|
case (state)
|
case (state)
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| Line 170... |
Line 217... |
FETCH_OP: begin
|
FETCH_OP: begin
|
next_state = FETCH_LOW;
|
next_state = FETCH_LOW;
|
end
|
end
|
FETCH_OP_CALC: begin
|
FETCH_OP_CALC: begin
|
next_state = FETCH_LOW;
|
next_state = FETCH_LOW;
|
alu_opcode = ir;
|
//alu_opcode = ir;
|
alu_enable = 1'b1;
|
//alu_enable = 1'b1;
|
end
|
end
|
FETCH_LOW: begin
|
FETCH_LOW: begin
|
if (accumulator || implied) begin
|
if (accumulator || implied) begin
|
alu_opcode = data_in;
|
//alu_opcode = data_in;
|
alu_enable = 1'b1;
|
//alu_enable = 1'b1;
|
next_state = FETCH_OP;
|
next_state = FETCH_OP;
|
end
|
end
|
else if (immediate) begin
|
else if (immediate) begin
|
next_state = FETCH_OP_CALC;
|
next_state = FETCH_OP_CALC;
|
end
|
end
|
| Line 210... |
Line 257... |
read = 1'b0;
|
read = 1'b0;
|
read_modify_write = 1'b0;
|
read_modify_write = 1'b0;
|
write = 1'b0;
|
write = 1'b0;
|
jump = 1'b0;
|
jump = 1'b0;
|
|
|
if (state == FETCH_LOW) begin
|
case (ir)
|
case (data_in)
|
|
BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
|
BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
|
PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
|
PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
|
implied = 1'b1;
|
implied = 1'b1;
|
end
|
end
|
ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
|
ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
|
| Line 273... |
Line 319... |
LDY_ZPX = 8'hB4,
|
LDY_ZPX = 8'hB4,
|
LDY_ABS = 8'hAC,
|
LDY_ABS = 8'hAC,
|
LDY_ABX = 8'hBC;
|
LDY_ABX = 8'hBC;
|
*/
|
*/
|
|
|
|
|
end
|
|
end // no way
|
end // no way
|
endmodule
|
endmodule
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