| Line 46... |
Line 46... |
//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module t6507lp_fsm(clk_in, rst_in_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
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module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
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parameter DATA_SIZE = 4'd8;
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parameter DATA_SIZE = 4'd8;
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parameter ADDR_SIZE = 4'd13;
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parameter ADDR_SIZE = 4'd13;
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input clk_in;
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input clk;
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input rst_in_n;
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input reset_n;
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input [DATA_SIZE-1:0] alu_result;
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input [DATA_SIZE-1:0] alu_result;
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input [DATA_SIZE-1:0] alu_status;
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input [DATA_SIZE-1:0] alu_status;
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input [DATA_SIZE-1:0] data_in;
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input [DATA_SIZE-1:0] data_in;
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output reg [ADDR_SIZE-1:0] address;
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output reg [ADDR_SIZE-1:0] address;
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output reg control; // one bit is enough? read = 0, write = 1
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output reg control; // one bit is enough? read = 0, write = 1
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| Line 70... |
Line 69... |
localparam RESET = 4'b1111;
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localparam RESET = 4'b1111;
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localparam FETCH_OP = 4'b0000;
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localparam FETCH_OP = 4'b0000;
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localparam FETCH_OP_CALC = 4'b0001;
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localparam FETCH_OP_CALC = 4'b0001;
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localparam FETCH_LOW = 4'b0010;
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localparam FETCH_LOW = 4'b0010;
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localparam FETCH_HIGH = 4'b0011;
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localparam FETCH_HIGH = 4'b0011;
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localparam READ_MEM = 4'b0100;
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localparam DUMMY_WRT_CALC = 4'b0101;
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localparam WRITE_MEM = 4'b0110;
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localparam FETCH_OP_CALC_PARAM = 4'b0111;
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// OPCODES TODO: verify how this get synthesised
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// OPCODES TODO: verify how this get synthesised
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`include "../T6507LP_Package.v"
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`include "../T6507LP_Package.v"
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// control signals
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// control signals
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| Line 81... |
Line 84... |
localparam MEM_WRITE = 1'b1;
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localparam MEM_WRITE = 1'b1;
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reg [ADDR_SIZE-1:0] pc; // program counter
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reg [ADDR_SIZE-1:0] pc; // program counter
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reg [DATA_SIZE-1:0] sp; // stack pointer
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reg [DATA_SIZE-1:0] sp; // stack pointer
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reg [DATA_SIZE-1:0] ir; // instruction register
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reg [DATA_SIZE-1:0] ir; // instruction register
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reg [ADDR_SIZE:0] temp_add; // temporary address
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reg [ADDR_SIZE:0] temp_addr; // temporary address
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reg [DATA_SIZE-1:0] temp_data; // temporary data
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reg [DATA_SIZE-1:0] temp_data; // temporary data
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reg [3:0] state, next_state; // current and next state registers
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reg [3:0] state, next_state; // current and next state registers
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// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
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// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
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| Line 107... |
Line 110... |
reg jump;
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reg jump;
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wire [ADDR_SIZE-1:0] next_pc;
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wire [ADDR_SIZE-1:0] next_pc;
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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always @ (posedge clk_in or negedge rst_in_n) begin // sequencial always block
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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if (rst_in_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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// TODO: all internal flip-flops must assume default values
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// all registers must assume default values
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
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sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
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ir <= 0;
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ir <= 0;
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temp_add <= 0;
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temp_addr <= 0;
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temp_data <= 0;
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temp_data <= 0;
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state <= RESET;
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state <= RESET;
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// registered outputs also receive default values
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address <= 0;
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control <= 0; // check if these 2 shouldnt be on the other always block along with the address
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data_out <= 0;
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end
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end
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else begin
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else begin
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state <= next_state;
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state <= next_state;
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control <= MEM_READ;
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case (state)
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case (state)
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RESET: begin
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RESET: begin
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// The processor was reset
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// The processor was reset
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end
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end
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FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
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FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
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// the last cycle was a memory write.
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// the last cycle was a memory write.
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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ir <= data_in;
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ir <= data_in;
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end
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end
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FETCH_OP_CALC: begin // this is the pipeline happening!
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FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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ir <= data_in;
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ir <= data_in;
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end
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end
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FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
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FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
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if (accumulator || implied) begin
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if (accumulator || implied) begin
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pc <= pc; // is this better?
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pc <= pc; // is this better?
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address <= pc;
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end
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end
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else if (immediate) begin
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else if (immediate) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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temp_data <= data_in; // the follow-up byte is saved in temp_data
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temp_data <= data_in; // the follow-up byte is saved in temp_data
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end
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end
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else if (absolute) begin
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pc <= next_pc;
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address <= next_pc;
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temp_addr[7:0] <= data_in;
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end
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end
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default: begin
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$finish(0);
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end
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end
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FETCH_HIGH: begin
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endcase
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if (jump) begin
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pc <= {data_in[4:0], temp_addr}; // PCL <= first byte, PCH <= second byte
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address <= {data_in[4:0], temp_addr};
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end
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end
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else begin
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if (write) begin
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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address <= {data_in[4:0],temp_addr[7:0]};
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control <= MEM_WRITE;
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end
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end
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else begin // read_modify_write or just read
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always @ (posedge clk_in or negedge rst_in_n) begin
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pc <= next_pc;
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if (rst_in_n == 1'b0) begin
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temp_addr[12:8] <= data_in[4:0];
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// TODO: all outputs must assume default values
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address <= {data_in[4:0],temp_addr[7:0]};
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address <= 0;
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control <= 0; // one bit is enough? read = 0, write = 1
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data_out <= 0;
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alu_opcode <= 0;
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alu_a <= 0;
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alu_enable <= 0;
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end
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end
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else begin
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address <= pc;
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case (state)
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RESET: begin
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// The processor was reset. No output whatsoever.
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end
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end
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FETCH_OP: begin
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//else begin
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// it is a simple fetch. no output change.
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// $write("FETCHHIGH PROBLEM");
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// $finish(0);
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//end
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end
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READ_MEM: begin
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if (read_modify_write) begin
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pc <= pc;
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address <= temp_addr;
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control <= MEM_WRITE;
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temp_data <= data_in;
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data_out <= data_in; // writeback the same value
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end
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end
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FETCH_OP_CALC: begin // this is the pipeline happening!
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else begin
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alu_opcode <= ir;
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pc <= pc;
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alu_a <= temp_data;
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address <= pc;
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alu_enable <= 1'b1;
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temp_data <= data_in;
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end
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end
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FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
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if (accumulator || implied) begin
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alu_opcode <= ir;
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alu_enable <= 1'b1;
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end
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end
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else begin // nothing?
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DUMMY_WRT_CALC: begin
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pc <= pc;
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address <= temp_addr;
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control <= MEM_WRITE;
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data_out <= alu_result;
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end
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end
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WRITE_MEM: begin
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pc <= pc;
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address <= pc;
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data_out = 8'hzz;
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end
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end
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default: begin
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default: begin
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$finish(0);
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$finish(0);
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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always @ (*) begin // this is the next_state logic always block
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always @ (*) begin // this is the next_state logic and the output logic always block
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//address = pc;
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//control = MEM_READ;
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//control = MEM_READ;
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//data_out = 8'h00;
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//data_out = 8'h00;
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//alu_opcode = 8'h00;
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//alu_a = 8'h00;
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alu_opcode = 8'h00;
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//alu_enable = 1'b0;
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alu_a = 8'h00;
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alu_enable = 1'b0;
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//address = pc;
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next_state = RESET; // this prevents the latch
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next_state = RESET; // this prevents the latch
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begin
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case (state)
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case (state)
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RESET: begin
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RESET: begin
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next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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FETCH_OP: begin
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FETCH_OP: begin
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next_state = FETCH_LOW;
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next_state = FETCH_LOW;
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//address = pc;
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end
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end
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FETCH_OP_CALC: begin
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FETCH_OP_CALC: begin
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next_state = FETCH_LOW;
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next_state = FETCH_LOW;
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//alu_opcode = ir;
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alu_opcode = ir;
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//alu_enable = 1'b1;
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alu_enable = 1'b1;
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//address = next_pc;
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end
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FETCH_OP_CALC_PARAM: begin
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next_state = FETCH_LOW;
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alu_opcode = ir;
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alu_enable = 1'b1;
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alu_a = temp_data;
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//address = next_pc;
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end
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end
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FETCH_LOW: begin
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FETCH_LOW: begin
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if (accumulator || implied) begin
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if (accumulator || implied) begin
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//alu_opcode = data_in;
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alu_opcode = ir;
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//alu_enable = 1'b1;
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alu_enable = 1'b1;
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next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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else if (immediate) begin
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else if (immediate) begin
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next_state = FETCH_OP_CALC;
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next_state = FETCH_OP_CALC_PARAM;
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end
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end
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else begin // at least the immediate address mode falls here
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else begin // at least the absolute address mode falls here
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next_state = FETCH_HIGH;
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next_state = FETCH_HIGH;
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end
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end
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//address = next_pc;
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end
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FETCH_HIGH: begin
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if (jump) begin
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next_state = FETCH_OP;
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end
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else if (read || read_modify_write) begin
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next_state = READ_MEM;
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end
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else if (write) begin
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next_state = WRITE_MEM;
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end
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else begin
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$write("unknown behavior");
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$finish(0);
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end
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end
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READ_MEM: begin
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if (read) begin
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next_state = FETCH_OP_CALC_PARAM;
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end
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else if (read_modify_write) begin
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next_state = DUMMY_WRT_CALC;
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end
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end
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DUMMY_WRT_CALC: begin
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alu_opcode = ir;
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alu_enable = 1'b1;
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alu_a = data_in;
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next_state = WRITE_MEM;
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end
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WRITE_MEM: begin
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next_state = FETCH_OP;
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end
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end
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default: begin
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default: begin
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next_state = RESET;
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next_state = RESET;
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end
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end
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endcase
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endcase
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end
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end
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end
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// this always block is responsible for updating the address mode
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// this always block is responsible for updating the address mode
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always @ (*) begin //
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always @ (*) begin //
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absolute = 1'b0;
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absolute = 1'b0;
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absolute_indexed = 1'b0;
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absolute_indexed = 1'b0;
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| Line 291... |
Line 353... |
end
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end
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ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
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ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
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ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
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ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
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indirect = 1'b1;
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indirect = 1'b1;
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end
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end
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default: begin
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$write("unknown OPCODE!");
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$finish();
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end
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endcase
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endcase
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if (data_in == JMP_ABS || data_in == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
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case (ir)
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jump = 1'b1;
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ASL_ACC, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ACC, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ACC, ROL_ZPG, ROL_ZPX, ROL_ABS,
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ROL_ABX, ROR_ACC, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS,
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DEC_ABX: begin
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read_modify_write = 1'b1;
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end
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end
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STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY, STX_ZPG, STX_ZPY, STX_ABS, STY_ZPG, STY_ZPX, STY_ABS: begin
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write = 1'b1;
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end
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default: begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes
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read = 1'b1;
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end
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endcase
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// if (data_in == )
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if (ir == JMP_ABS || ir == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
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jump = 1'b1;
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/*LDA_IMM = 8'hA9,
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end
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LDA_ZPG = 8'hA5,
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LDA_ZPX = 8'hB5,
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LDA_ABS = 8'hAD,
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LDA_ABX = 8'hBD,
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LDA_ABY = 8'hB9,
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LDA_IDX = 8'hA1,
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LDA_IDY = 8'hB1;
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LDX_IMM = 8'hA2,
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LDX_ZPG = 8'hA6,
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LDX_ZPY = 8'hB6,
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LDX_ABS = 8'hAE,
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LDX_ABY = 8'hBE;
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LDY_IMM = 8'hA0,
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LDY_ZPG = 8'hA4,
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LDY_ZPX = 8'hB4,
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LDY_ABS = 8'hAC,
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LDY_ABX = 8'hBC;
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*/
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end // no way
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end // no way
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endmodule
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endmodule
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