| Line 127... |
Line 127... |
data_out <= 0;
|
data_out <= 0;
|
end
|
end
|
else begin
|
else begin
|
state <= next_state;
|
state <= next_state;
|
control <= MEM_READ;
|
control <= MEM_READ;
|
|
data_out = 8'hZ;
|
case (state)
|
case (state)
|
RESET: begin
|
RESET: begin
|
// The processor was reset
|
// The processor was reset
|
end
|
end
|
FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
|
FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
|
| Line 158... |
Line 158... |
else if (absolute) begin
|
else if (absolute) begin
|
pc <= next_pc;
|
pc <= next_pc;
|
address <= next_pc;
|
address <= next_pc;
|
temp_addr[7:0] <= data_in;
|
temp_addr[7:0] <= data_in;
|
end
|
end
|
|
else if (zero_page) begin
|
|
pc <= next_pc;
|
|
address <= {{5{1'b0}},data_in};
|
|
if (write) begin
|
|
control <= MEM_WRITE;
|
|
end
|
|
end
|
end
|
end
|
FETCH_HIGH: begin
|
FETCH_HIGH: begin
|
if (jump) begin
|
if (jump) begin
|
pc <= {data_in[4:0], temp_addr}; // PCL <= first byte, PCH <= second byte
|
pc <= {data_in[4:0], temp_addr}; // PCL <= first byte, PCH <= second byte
|
address <= {data_in[4:0], temp_addr};
|
address <= {data_in[4:0], temp_addr};
|
| Line 170... |
Line 177... |
if (write) begin
|
if (write) begin
|
pc <= next_pc;
|
pc <= next_pc;
|
temp_addr[12:8] <= data_in[4:0];
|
temp_addr[12:8] <= data_in[4:0];
|
address <= {data_in[4:0],temp_addr[7:0]};
|
address <= {data_in[4:0],temp_addr[7:0]};
|
control <= MEM_WRITE;
|
control <= MEM_WRITE;
|
|
data_out <= alu_result;
|
end
|
end
|
else begin // read_modify_write or just read
|
else begin // read_modify_write or just read
|
pc <= next_pc;
|
pc <= next_pc;
|
temp_addr[12:8] <= data_in[4:0];
|
temp_addr[12:8] <= data_in[4:0];
|
address <= {data_in[4:0],temp_addr[7:0]};
|
address <= {data_in[4:0],temp_addr[7:0]};
|
| Line 205... |
Line 213... |
data_out <= alu_result;
|
data_out <= alu_result;
|
end
|
end
|
WRITE_MEM: begin
|
WRITE_MEM: begin
|
pc <= pc;
|
pc <= pc;
|
address <= pc;
|
address <= pc;
|
data_out = 8'hzz;
|
|
end
|
end
|
default: begin
|
default: begin
|
$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
|
$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
|
$finish(0);
|
$finish(0);
|
end
|
end
|
| Line 233... |
Line 240... |
RESET: begin
|
RESET: begin
|
next_state = FETCH_OP;
|
next_state = FETCH_OP;
|
end
|
end
|
FETCH_OP: begin
|
FETCH_OP: begin
|
next_state = FETCH_LOW;
|
next_state = FETCH_LOW;
|
//address = pc;
|
|
end
|
end
|
FETCH_OP_CALC: begin
|
FETCH_OP_CALC: begin
|
next_state = FETCH_LOW;
|
next_state = FETCH_LOW;
|
alu_opcode = ir;
|
alu_opcode = ir;
|
alu_enable = 1'b1;
|
alu_enable = 1'b1;
|
//address = next_pc;
|
|
|
|
end
|
end
|
FETCH_OP_CALC_PARAM: begin
|
FETCH_OP_CALC_PARAM: begin
|
next_state = FETCH_LOW;
|
next_state = FETCH_LOW;
|
alu_opcode = ir;
|
alu_opcode = ir;
|
alu_enable = 1'b1;
|
alu_enable = 1'b1;
|
alu_a = temp_data;
|
alu_a = temp_data;
|
//address = next_pc;
|
|
end
|
end
|
FETCH_LOW: begin
|
FETCH_LOW: begin
|
if (accumulator || implied) begin
|
if (accumulator || implied) begin
|
alu_opcode = ir;
|
alu_opcode = ir;
|
alu_enable = 1'b1;
|
alu_enable = 1'b1;
|
next_state = FETCH_OP;
|
next_state = FETCH_OP;
|
end
|
end
|
else if (immediate) begin
|
else if (immediate) begin
|
next_state = FETCH_OP_CALC_PARAM;
|
next_state = FETCH_OP_CALC_PARAM;
|
end
|
end
|
|
else if (zero_page) begin
|
|
if (read || read_modify_write) begin
|
|
next_state = READ_MEM;
|
|
end
|
|
else if (write) begin
|
|
next_state = WRITE_MEM;
|
|
end
|
|
else begin
|
|
$write("unknown behavior");
|
|
$finish(0);
|
|
end
|
|
end
|
else begin // at least the absolute address mode falls here
|
else begin // at least the absolute address mode falls here
|
next_state = FETCH_HIGH;
|
next_state = FETCH_HIGH;
|
end
|
end
|
//address = next_pc;
|
|
|
|
end
|
end
|
FETCH_HIGH: begin
|
FETCH_HIGH: begin
|
if (jump) begin
|
if (jump) begin
|
next_state = FETCH_OP;
|
next_state = FETCH_OP;
|
end
|
end
|
| Line 302... |
Line 316... |
next_state = RESET;
|
next_state = RESET;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
// this always block is responsible for updating the address mode
|
// this always block is responsible for updating the address mode and the type of operation being done
|
always @ (*) begin //
|
always @ (*) begin //
|
absolute = 1'b0;
|
absolute = 1'b0;
|
absolute_indexed = 1'b0;
|
absolute_indexed = 1'b0;
|
accumulator = 1'b0;
|
accumulator = 1'b0;
|
immediate = 1'b0;
|
immediate = 1'b0;
|
| Line 354... |
Line 368... |
ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
|
ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
|
ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
|
ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
|
indirect = 1'b1;
|
indirect = 1'b1;
|
end
|
end
|
default: begin
|
default: begin
|
$write("unknown OPCODE!");
|
$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
|
$finish();
|
$finish();
|
end
|
end
|
endcase
|
endcase
|
|
|
case (ir)
|
case (ir)
|
