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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Diff between revs 77 and 78
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| Rev 77 |
Rev 78 |
| Line 161... |
Line 161... |
temp_addr[7:0] <= data_in;
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temp_addr[7:0] <= data_in;
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end
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end
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else if (zero_page) begin
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else if (zero_page) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= {{5{1'b0}},data_in};
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address <= {{5{1'b0}},data_in};
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temp_addr <= {{5{1'b0}},data_in};
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if (write) begin
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if (write) begin
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control <= MEM_WRITE;
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control <= MEM_WRITE;
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data_out <= alu_result;
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end
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end
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end
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end
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end
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end
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FETCH_HIGH: begin
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FETCH_HIGH: begin
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if (jump) begin
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if (jump) begin
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| Line 277... |
Line 280... |
end
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end
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end
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end
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else begin // at least the absolute address mode falls here
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else begin // at least the absolute address mode falls here
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next_state = FETCH_HIGH;
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next_state = FETCH_HIGH;
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end
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end
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if (write) begin
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alu_opcode = ir;
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alu_enable = 1'b1;
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alu_a = 8'hzz;
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end
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end
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end
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FETCH_HIGH: begin
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FETCH_HIGH: begin
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if (jump) begin
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if (jump) begin
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next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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