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module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
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module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
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parameter DATA_SIZE = 4'h8;
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parameter DATA_SIZE = 4'h8;
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parameter ADDR_SIZE = 4'hd;
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parameter ADDR_SIZE = 4'hd;
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localparam DATA_SIZE_ = DATA_SIZE - 1'b1;
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localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;
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localparam ADDR_SIZE_ = ADDR_SIZE - 1'b1;
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localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
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input clk;
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input clk;
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input reset_n;
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input reset_n;
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input [DATA_SIZE_:0] alu_result;
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input [DATA_SIZE_:0] alu_result;
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input [DATA_SIZE_:0] alu_status;
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input [DATA_SIZE_:0] alu_status;
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control <= MEM_READ;
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control <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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else begin
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else begin
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state <= next_state;
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state <= next_state;
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control <= MEM_READ;
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data_out <= 8'h00;
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case (state)
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case (state)
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RESET: begin
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RESET: begin
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// The processor was reset
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// The processor was reset
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$write("under reset");
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$write("under reset");
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end
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end
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FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
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FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
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// the last cycle was a memory write.
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// the last cycle was a memory write.
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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ir <= data_in;
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ir <= data_in;
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end
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end
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FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
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FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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ir <= data_in;
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ir <= data_in;
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end
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end
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FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
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FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
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if (accumulator || implied) begin
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if (accumulator || implied) begin
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pc <= pc; // is this better?
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pc <= pc; // is this better?
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address <= pc;
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address <= pc;
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control <= MEM_READ;
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end
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end
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else if (immediate) begin
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else if (immediate) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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temp_data <= data_in; // the follow-up byte is saved in temp_data
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temp_data <= data_in; // the follow-up byte is saved in temp_data
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end
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end
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else if (absolute) begin
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else if (absolute) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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temp_addr[7:0] <= data_in;
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temp_addr[7:0] <= data_in;
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end
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end
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else if (zero_page) begin
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else if (zero_page) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= {{5{1'b0}},data_in};
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address <= {{5{1'b0}},data_in};
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if (write) begin
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if (write) begin
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control <= MEM_WRITE;
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control <= MEM_WRITE;
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data_out <= alu_result;
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data_out <= alu_result;
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end
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end
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else begin
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control <= MEM_READ;
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data_out <= 8'h00;
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end
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end
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end
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end
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end
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FETCH_HIGH: begin
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FETCH_HIGH: begin
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if (jump) begin
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if (jump) begin
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pc <= {data_in[4:0], temp_addr}; // PCL <= first byte, PCH <= second byte
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pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
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address <= {data_in[4:0], temp_addr};
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address <= {data_in[4:0], temp_addr[7:0]};
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control <= MEM_READ;
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data_out <= 8'h00;
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end
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end
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else begin
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else begin
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if (write) begin
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if (write) begin
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pc <= next_pc;
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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temp_addr[12:8] <= data_in[4:0];
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end
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end
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else begin // read_modify_write or just read
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else begin // read_modify_write or just read
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pc <= next_pc;
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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temp_addr[12:8] <= data_in[4:0];
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address <= {data_in[4:0],temp_addr[7:0]};
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address <= {data_in[4:0],temp_addr[7:0]};
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control <= MEM_READ;
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data_out <= 8'h00;
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end
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end
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end
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end
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//else begin
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//else begin
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// $write("FETCHHIGH PROBLEM");
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// $write("FETCHHIGH PROBLEM");
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// $finish(0);
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// $finish(0);
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end
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end
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else begin
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else begin
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pc <= pc;
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pc <= pc;
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address <= pc;
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address <= pc;
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temp_data <= data_in;
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temp_data <= data_in;
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control <= MEM_READ;
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data_out <= 8'h00;
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end
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end
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end
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end
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DUMMY_WRT_CALC: begin
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DUMMY_WRT_CALC: begin
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pc <= pc;
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pc <= pc;
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address <= temp_addr;
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address <= temp_addr;
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data_out <= alu_result;
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data_out <= alu_result;
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end
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end
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WRITE_MEM: begin
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WRITE_MEM: begin
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pc <= pc;
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pc <= pc;
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address <= pc;
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address <= pc;
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control <= MEM_READ;
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data_out <= 8'h00;
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end
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end
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default: begin
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default: begin
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$finish(0);
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$finish(0);
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end
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end
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