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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
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module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
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parameter DATA_SIZE = 4'h8;
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parameter DATA_SIZE = 4'h8;
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parameter ADDR_SIZE = 4'hd;
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parameter ADDR_SIZE = 4'hd;
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localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;
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localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;
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localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
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localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
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Line 65... |
output reg [DATA_SIZE_:0] data_out;
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output reg [DATA_SIZE_:0] data_out;
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output reg [DATA_SIZE_:0] alu_opcode;
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output reg [DATA_SIZE_:0] alu_opcode;
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output reg [DATA_SIZE_:0] alu_a;
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output reg [DATA_SIZE_:0] alu_a;
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output reg alu_enable;
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output reg alu_enable;
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input [DATA_SIZE_:0] alu_x;
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input [DATA_SIZE_:0] alu_y;
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// FSM states
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// FSM states
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localparam RESET = 4'b1111;
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localparam RESET = 4'b1111;
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localparam FETCH_OP = 4'b0000;
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localparam FETCH_OP = 4'b0000;
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localparam FETCH_OP_CALC = 4'b0001;
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localparam FETCH_OP_CALC = 4'b0001;
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Line 79... |
localparam FETCH_HIGH = 4'b0011;
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localparam FETCH_HIGH = 4'b0011;
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localparam READ_MEM = 4'b0100;
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localparam READ_MEM = 4'b0100;
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localparam DUMMY_WRT_CALC = 4'b0101;
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localparam DUMMY_WRT_CALC = 4'b0101;
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localparam WRITE_MEM = 4'b0110;
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localparam WRITE_MEM = 4'b0110;
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localparam FETCH_OP_CALC_PARAM = 4'b0111;
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localparam FETCH_OP_CALC_PARAM = 4'b0111;
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localparam READ_MEM_CALC_INDEX = 4'b1000;
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// OPCODES TODO: verify how this get synthesised
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// OPCODES TODO: verify how this get synthesised
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`include "../T6507LP_Package.v"
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`include "../T6507LP_Package.v"
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// control signals
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// control signals
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Line 107... |
reg implied;
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reg implied;
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reg indirect;
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reg indirect;
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reg relative;
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reg relative;
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reg zero_page;
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reg zero_page;
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reg zero_page_indexed;
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reg zero_page_indexed;
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reg [DATA_SIZE_:0] index; // will be assigned with either X or Y
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// regs that store the type of operation. again, this simplifies the FSM a lot.
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// regs that store the type of operation. again, this simplifies the FSM a lot.
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reg read;
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reg read;
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reg read_modify_write;
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reg read_modify_write;
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reg write;
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reg write;
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reg jump;
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reg jump;
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wire [ADDR_SIZE_:0] next_pc;
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wire [ADDR_SIZE_:0] next_pc;
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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wire [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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// so the assign was changed to conditional.
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assign address_plus_index = (zero_page_indexed == 1'b1 && state == READ_MEM_CALC_INDEX)? (temp_addr + index): 0;
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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// all registers must assume default values
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// all registers must assume default values
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
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sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
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Line 189... |
else begin
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else begin
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control <= MEM_READ;
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control <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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end
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end
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else if (zero_page_indexed) begin
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pc <= next_pc;
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address <= {{5{1'b0}},data_in};
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temp_addr <= {{5{1'b0}},data_in};
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control <= MEM_READ;
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end
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end
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end
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FETCH_HIGH: begin
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FETCH_HIGH: begin
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if (jump) begin
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if (jump) begin
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pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
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pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
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address <= {data_in[4:0], temp_addr[7:0]};
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address <= {data_in[4:0], temp_addr[7:0]};
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Line 240... |
temp_data <= data_in;
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temp_data <= data_in;
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control <= MEM_READ;
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control <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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end
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end
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READ_MEM_CALC_INDEX: begin
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//pc <= next_pc; // pc was already updated in the previous cycle
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address <= address_plus_index;
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temp_addr <= address_plus_index;
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if (write) begin
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control <= MEM_WRITE;
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data_out <= alu_result;
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end
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else begin
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control <= MEM_READ;
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data_out <= 8'h00;
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end
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end
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DUMMY_WRT_CALC: begin
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DUMMY_WRT_CALC: begin
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pc <= pc;
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pc <= pc;
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address <= temp_addr;
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address <= temp_addr;
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control <= MEM_WRITE;
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control <= MEM_WRITE;
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data_out <= alu_result;
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data_out <= alu_result;
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Line 316... |
if (read || read_modify_write) begin
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if (read || read_modify_write) begin
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next_state = READ_MEM;
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next_state = READ_MEM;
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end
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end
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else if (write) begin
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else if (write) begin
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next_state = WRITE_MEM;
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next_state = WRITE_MEM;
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alu_opcode = ir;
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alu_enable = 1'b1;
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alu_a = 8'h00;
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end
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end
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else begin
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else begin
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$write("unknown behavior");
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$write("unknown behavior");
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$finish(0);
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$finish(0);
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end
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end
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end
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end
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else if (zero_page_indexed) begin
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next_state = READ_MEM_CALC_INDEX;
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end
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else begin // at least the absolute address mode falls here
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else begin // at least the absolute address mode falls here
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next_state = FETCH_HIGH;
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next_state = FETCH_HIGH;
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end
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if (write) begin // this is being done one cycle early?
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if (write) begin
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alu_opcode = ir;
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alu_opcode = ir;
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alu_enable = 1'b1;
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alu_enable = 1'b1;
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alu_a = 8'h00;
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alu_a = 8'h00;
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end
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end
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end
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end
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end
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FETCH_HIGH: begin
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FETCH_HIGH: begin
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if (jump) begin
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if (jump) begin
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next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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Line 352... |
else begin
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else begin
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$write("unknown behavior");
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$write("unknown behavior");
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$finish(0);
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$finish(0);
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end
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end
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end
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end
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READ_MEM_CALC_INDEX: begin
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if (read || read_modify_write) begin
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next_state = READ_MEM;
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end
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else if (write) begin
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alu_opcode = ir;
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alu_enable = 1'b1;
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next_state = WRITE_MEM;
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end
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else begin
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$write("unknown behavior");
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$finish(0);
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end
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end
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READ_MEM: begin
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READ_MEM: begin
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if (read) begin
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if (read) begin
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next_state = FETCH_OP_CALC_PARAM;
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next_state = FETCH_OP_CALC_PARAM;
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end
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end
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else if (read_modify_write) begin
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else if (read_modify_write) begin
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Line 401... |
indirect = 1'b0;
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indirect = 1'b0;
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relative = 1'b0;
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relative = 1'b0;
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zero_page = 1'b0;
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zero_page = 1'b0;
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zero_page_indexed = 1'b0;
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zero_page_indexed = 1'b0;
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index = 1'b0;
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read = 1'b0;
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read = 1'b0;
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read_modify_write = 1'b0;
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read_modify_write = 1'b0;
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write = 1'b0;
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write = 1'b0;
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jump = 1'b0;
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jump = 1'b0;
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Line 424... |
ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
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ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
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LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
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LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
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zero_page = 1'b1;
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zero_page = 1'b1;
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end
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end
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ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
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ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
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SBC_ZPX, STA_ZPX, LDX_ZPY, STX_ZPY, STY_ZPX: begin
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SBC_ZPX, STA_ZPX, STY_ZPX: begin
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zero_page_indexed = 1'b1;
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index = alu_x;
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end
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LDX_ZPY, STX_ZPY: begin
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zero_page_indexed = 1'b1;
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zero_page_indexed = 1'b1;
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index = alu_y;
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end
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end
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BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin
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BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin
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relative = 1'b1;
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relative = 1'b1;
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end
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end
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ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,
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ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,
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Line 448... |
ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
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ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
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ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
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ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
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indirect = 1'b1;
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indirect = 1'b1;
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end
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end
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default: begin
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default: begin
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if (reset_n == 1) begin // the processor is NOT being reset
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$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
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$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
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$finish();
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$finish();
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end
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end
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end
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endcase
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endcase
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case (ir)
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case (ir)
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ASL_ACC, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ACC, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ACC, ROL_ZPG, ROL_ZPX, ROL_ABS,
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ASL_ACC, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ACC, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ACC, ROL_ZPG, ROL_ZPX, ROL_ABS,
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ROL_ABX, ROR_ACC, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS,
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ROL_ABX, ROR_ACC, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS,
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| Line 416... |
Line 472... |
endcase
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endcase
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if (ir == JMP_ABS || ir == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
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if (ir == JMP_ABS || ir == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
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jump = 1'b1;
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jump = 1'b1;
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end
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end
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end // no way
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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