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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
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module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
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parameter DATA_SIZE = 4'h8;
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parameter DATA_SIZE = 8;
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parameter ADDR_SIZE = 4'hd;
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parameter ADDR_SIZE = 13;
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localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;
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localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;
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localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
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localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
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input clk;
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input clk;
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output reg alu_enable;
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output reg alu_enable;
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input [DATA_SIZE_:0] alu_x;
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input [DATA_SIZE_:0] alu_x;
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input [DATA_SIZE_:0] alu_y;
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input [DATA_SIZE_:0] alu_y;
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// FSM states
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// FSM states
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localparam RESET = 4'b1111;
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localparam FETCH_OP = 4'b0000;
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localparam FETCH_OP = 4'b0000;
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localparam FETCH_OP_CALC = 4'b0001;
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localparam FETCH_OP_CALC = 4'b0001;
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localparam FETCH_LOW = 4'b0010;
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localparam FETCH_LOW = 4'b0010;
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localparam FETCH_HIGH = 4'b0011;
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localparam FETCH_HIGH = 4'b0011;
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localparam READ_MEM = 4'b0100;
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localparam READ_MEM = 4'b0100;
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localparam DUMMY_WRT_CALC = 4'b0101;
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localparam DUMMY_WRT_CALC = 4'b0101;
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localparam WRITE_MEM = 4'b0110;
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localparam WRITE_MEM = 4'b0110;
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localparam FETCH_OP_CALC_PARAM = 4'b0111;
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localparam FETCH_OP_CALC_PARAM = 4'b0111;
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localparam READ_MEM_CALC_INDEX = 4'b1000;
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localparam READ_MEM_CALC_INDEX = 4'b1000;
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localparam FETCH_HIGH_CALC_INDEX = 4'b1001;
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localparam READ_MEM_FIX_ADDR = 4'b1010;
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localparam RESET = 4'b1111;
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// OPCODES TODO: verify how this get synthesised
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// OPCODES TODO: verify how this get synthesised
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`include "../T6507LP_Package.v"
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`include "../T6507LP_Package.v"
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// control signals
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// control signals
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reg jump;
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reg jump;
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wire [ADDR_SIZE_:0] next_pc;
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wire [ADDR_SIZE_:0] next_pc;
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assign next_pc = pc + 13'b0000000000001;
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assign next_pc = pc + 13'b0000000000001;
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wire [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
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// so the assign was changed to conditional.
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reg page_crossed; // so the simple assign was changed into a combinational always block
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assign address_plus_index = (zero_page_indexed == 1'b1 && state == READ_MEM_CALC_INDEX)? (temp_addr + index): 0;
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always @(*) begin
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address_plus_index = 0;
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page_crossed = 0;
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if (state == READ_MEM_CALC_INDEX || state == FETCH_HIGH_CALC_INDEX) begin
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{page_crossed, address_plus_index} = temp_addr + index;
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end
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end
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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// all registers must assume default values
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// all registers must assume default values
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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control <= MEM_READ;
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temp_data <= data_in; // the follow-up byte is saved in temp_data
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temp_data <= data_in; // the follow-up byte is saved in temp_data
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end
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end
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else if (absolute) begin
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else if (absolute || absolute_indexed) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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control <= MEM_READ;
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temp_addr[7:0] <= data_in;
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temp_addr <= {{5{1'b0}},data_in};
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end
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end
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else if (zero_page) begin
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else if (zero_page) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= {{5{1'b0}},data_in};
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address <= {{5{1'b0}},data_in};
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temp_addr <= {{5{1'b0}},data_in};
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temp_addr <= {{5{1'b0}},data_in};
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address <= {{5{1'b0}},data_in};
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address <= {{5{1'b0}},data_in};
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temp_addr <= {{5{1'b0}},data_in};
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temp_addr <= {{5{1'b0}},data_in};
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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end
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end
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FETCH_HIGH_CALC_INDEX: begin
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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address <= {data_in[4:0], address_plus_index[7:0]};
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control <= MEM_READ;
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data_out <= 8'h00;
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end
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FETCH_HIGH: begin
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FETCH_HIGH: begin
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if (jump) begin
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if (jump) begin
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pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
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pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
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address <= {data_in[4:0], temp_addr[7:0]};
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address <= {data_in[4:0], temp_addr[7:0]};
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control <= MEM_READ;
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control <= MEM_READ;
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control <= MEM_READ;
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control <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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end
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end
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READ_MEM_FIX_ADDR: begin
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if (read) begin
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control <= MEM_READ;
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data_out <= 8'h00;
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if (page_crossed) begin
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address <= address_plus_index;
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temp_addr <= address_plus_index;
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end
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else begin
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address <= pc;
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temp_data <= data_in;
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end
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end
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else if (write) begin
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control <= MEM_WRITE;
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data_out <= alu_result;
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address <= address_plus_index;
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temp_addr <= address_plus_index;
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end
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else begin // read modify write
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control <= MEM_READ;
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data_out <= 8'h00;
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address <= address_plus_index;
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temp_addr <= address_plus_index;
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end
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end
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DUMMY_WRT_CALC: begin
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DUMMY_WRT_CALC: begin
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pc <= pc;
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pc <= pc;
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address <= temp_addr;
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address <= temp_addr;
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control <= MEM_WRITE;
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control <= MEM_WRITE;
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data_out <= alu_result;
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data_out <= alu_result;
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Line 372... |
end
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end
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end
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end
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else if (zero_page_indexed) begin
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else if (zero_page_indexed) begin
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next_state = READ_MEM_CALC_INDEX;
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next_state = READ_MEM_CALC_INDEX;
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end
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end
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else begin // at least the absolute address mode falls here
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else if (absolute) begin // at least the absolute address mode falls here
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next_state = FETCH_HIGH;
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next_state = FETCH_HIGH;
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if (write) begin // this is being done one cycle early?
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if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly
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alu_opcode = ir;
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alu_opcode = ir;
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alu_enable = 1'b1;
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alu_enable = 1'b1;
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alu_a = 8'h00;
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alu_a = 8'h00;
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end
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end
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end
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end
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else if (absolute_indexed) begin
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next_state = FETCH_HIGH_CALC_INDEX;
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end
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end
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FETCH_HIGH_CALC_INDEX: begin
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next_state = READ_MEM_FIX_ADDR;
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end
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READ_MEM_FIX_ADDR: begin
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if (read) begin
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if (page_crossed) begin
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next_state = READ_MEM;
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end
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else begin
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next_state = FETCH_OP_CALC_PARAM;
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end
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end
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else if (read_modify_write) begin
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next_state = READ_MEM;
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end
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else if (write) begin
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next_state = WRITE_MEM;
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end
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else begin
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$write("unknown behavior");
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$finish(0);
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end
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end
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end
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FETCH_HIGH: begin
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FETCH_HIGH: begin
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if (jump) begin
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if (jump) begin
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next_state = FETCH_OP;
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next_state = FETCH_OP;
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end
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end
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ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,
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ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,
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LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
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LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
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absolute = 1'b1;
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absolute = 1'b1;
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end
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end
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ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
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ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
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SBC_ABX, STA_ABX, ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
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SBC_ABX, STA_ABX: begin
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absolute_indexed = 1'b1;
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absolute_indexed = 1'b1;
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index = alu_x;
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end
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ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
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absolute_indexed = 1'b1;
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index = alu_y;
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end
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end
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ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
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ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
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ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
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ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
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indirect = 1'b1;
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indirect = 1'b1;
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end
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end
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