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Line 7... |
//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 6507 FSM ////
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//// 6507 FSM ////
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//// ////
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//// ////
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//// TODO: ////
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//// TODO: ////
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//// - Fix absolute indexed mode ////
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//// - Code the relative mode ////
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//// - Code the indexed indirect mode ////
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//// - Code the indexed indirect mode ////
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//// - Code the indirect indexed mode ////
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//// - Code the indirect indexed mode ////
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//// - Code the absolute indirect mode ////
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//// - Code the absolute indirect mode ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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| Line 69... |
Line 67... |
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input [DATA_SIZE_:0] alu_x;
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input [DATA_SIZE_:0] alu_x;
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input [DATA_SIZE_:0] alu_y;
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input [DATA_SIZE_:0] alu_y;
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// FSM states
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// FSM states
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localparam FETCH_OP = 4'b0000;
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localparam FETCH_OP = 5'b00000;
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localparam FETCH_OP_CALC = 4'b0001;
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localparam FETCH_OP_CALC = 5'b00001;
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localparam FETCH_LOW = 4'b0010;
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localparam FETCH_LOW = 5'b00010;
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localparam FETCH_HIGH = 4'b0011;
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localparam FETCH_HIGH = 5'b00011;
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localparam READ_MEM = 4'b0100;
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localparam READ_MEM = 5'b00100;
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localparam DUMMY_WRT_CALC = 4'b0101;
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localparam DUMMY_WRT_CALC = 5'b00101;
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localparam WRITE_MEM = 4'b0110;
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localparam WRITE_MEM = 5'b00110;
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localparam FETCH_OP_CALC_PARAM = 4'b0111;
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localparam FETCH_OP_CALC_PARAM = 5'b00111;
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localparam READ_MEM_CALC_INDEX = 4'b1000;
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localparam READ_MEM_CALC_INDEX = 5'b01000;
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localparam FETCH_HIGH_CALC_INDEX = 4'b1001;
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localparam FETCH_HIGH_CALC_INDEX = 5'b01001;
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localparam READ_MEM_FIX_ADDR = 4'b1010;
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localparam READ_MEM_FIX_ADDR = 5'b01010;
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localparam FETCH_OP_EVAL_BRANCH = 4'b1011;
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localparam FETCH_OP_EVAL_BRANCH = 5'b01011;
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localparam FETCH_OP_FIX_PC = 4'b1100;
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localparam FETCH_OP_FIX_PC = 5'b01100;
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localparam RESET = 4'b1111;
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localparam READ_FROM_POINTER = 5'b01101;
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localparam READ_FROM_POINTER_X = 5'b01110;
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localparam READ_FROM_POINTER_X1 = 5'b01111;
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localparam RESET = 5'b11111;
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// OPCODES TODO: verify how this get synthesised
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// OPCODES TODO: verify how this get synthesised
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`include "../T6507LP_Package.v"
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`include "../T6507LP_Package.v"
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// control signals
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// control signals
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| Line 106... |
Line 108... |
reg absolute;
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reg absolute;
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reg absolute_indexed;
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reg absolute_indexed;
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reg accumulator;
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reg accumulator;
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reg immediate;
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reg immediate;
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reg implied;
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reg implied;
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reg indirect;
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reg indirectx;
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reg indirecty;
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reg relative;
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reg relative;
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reg zero_page;
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reg zero_page;
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reg zero_page_indexed;
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reg zero_page_indexed;
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reg [DATA_SIZE_:0] index; // will be assigned with either X or Y
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reg [DATA_SIZE_:0] index; // will be assigned with either X or Y
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| Line 140... |
Line 143... |
if (state == FETCH_OP_FIX_PC || state == FETCH_OP_EVAL_BRANCH) begin
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if (state == FETCH_OP_FIX_PC || state == FETCH_OP_EVAL_BRANCH) begin
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{page_crossed, address_plus_index[7:0]} = pc[7:0] + index;
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{page_crossed, address_plus_index[7:0]} = pc[7:0] + index;
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address_plus_index[12:8] = pc[12:8] + page_crossed;// warning: pc might feed these lines twice and cause branch failure
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address_plus_index[12:8] = pc[12:8] + page_crossed;// warning: pc might feed these lines twice and cause branch failure
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end // solution: add a temp reg i guess
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end // solution: add a temp reg i guess
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end
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end
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else if (state == READ_FROM_POINTER) begin
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{page_crossed, address_plus_index[7:0]} = temp_data + index;
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address_plus_index[12:8] = 5'b00000;
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end
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else if (state == READ_FROM_POINTER_X) begin
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{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;
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address_plus_index[12:8] = 5'b00000;
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end
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end
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end
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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// all registers must assume default values
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// all registers must assume default values
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Line 226... |
pc <= next_pc;
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pc <= next_pc;
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address <= {{5{1'b0}}, data_in};
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address <= {{5{1'b0}}, data_in};
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temp_addr <= {{5{1'b0}}, data_in};
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temp_addr <= {{5{1'b0}}, data_in};
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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else if (indirectx) begin
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pc <= next_pc;
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address <= data_in;
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temp_data <= data_in;
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control <= MEM_READ;
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end
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end
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end
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FETCH_HIGH_CALC_INDEX: begin
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FETCH_HIGH_CALC_INDEX: begin
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pc <= next_pc;
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pc <= next_pc;
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temp_addr[12:8] <= data_in[4:0];
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temp_addr[12:8] <= data_in[4:0];
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address <= {data_in[4:0], address_plus_index[7:0]};
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address <= {data_in[4:0], address_plus_index[7:0]};
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| Line 235... |
Line 252... |
else begin
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else begin
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pc <= next_pc;
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pc <= next_pc;
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address <= next_pc;
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address <= next_pc;
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control <= MEM_READ;
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control <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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ir <= data_in;
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end
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end
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end
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end
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FETCH_OP_FIX_PC: begin
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FETCH_OP_FIX_PC: begin
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if (page_crossed) begin
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if (page_crossed) begin
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pc[12:8] <= address_plus_index[12:8];
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pc[12:8] <= address_plus_index[12:8];
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| Line 348... |
Line 366... |
pc <= pc;
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pc <= pc;
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address <= pc;
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address <= pc;
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control <= MEM_READ;
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control <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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READ_FROM_POINTER: begin
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pc <= pc;
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address <= address_plus_index;
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//temp_addr[7:0] <= data_in;
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control <= MEM_READ;
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end
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READ_FROM_POINTER_X: begin
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pc <= pc;
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address <= address_plus_index;
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temp_addr[7:0] <= data_in;
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control <= MEM_READ;
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end
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READ_FROM_POINTER_X1: begin
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pc <= pc;
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address <= {data_in[5:0], temp_addr[7:0]};
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if (write) begin
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control <= MEM_WRITE;
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end
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else begin
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control <= MEM_READ;
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end
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end
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default: begin
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default: begin
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$finish(0);
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$finish(0);
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end
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end
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| Line 423... |
Line 463... |
next_state = FETCH_HIGH_CALC_INDEX;
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next_state = FETCH_HIGH_CALC_INDEX;
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end
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end
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else if (relative) begin
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else if (relative) begin
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next_state = FETCH_OP_EVAL_BRANCH;
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next_state = FETCH_OP_EVAL_BRANCH;
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end
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end
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else if (indirectx) begin
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next_state = READ_FROM_POINTER;
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end
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end
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READ_FROM_POINTER: begin
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next_state = READ_FROM_POINTER_X;
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end
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READ_FROM_POINTER_X: begin
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next_state = READ_FROM_POINTER_X1;
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end
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READ_FROM_POINTER_X1: begin
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if (read || read_modify_write) begin
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next_state = READ_MEM;
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end
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else if (write) begin
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alu_opcode = ir;
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alu_enable = 1'b1;
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next_state = WRITE_MEM;
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end
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end
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end
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FETCH_OP_EVAL_BRANCH: begin
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FETCH_OP_EVAL_BRANCH: begin
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if (branch) begin
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if (branch) begin
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next_state = FETCH_OP_FIX_PC;
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next_state = FETCH_OP_FIX_PC;
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end
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end
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| Line 522... |
Line 581... |
absolute = 1'b0;
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absolute = 1'b0;
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absolute_indexed = 1'b0;
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absolute_indexed = 1'b0;
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accumulator = 1'b0;
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accumulator = 1'b0;
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immediate = 1'b0;
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immediate = 1'b0;
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implied = 1'b0;
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implied = 1'b0;
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indirect = 1'b0;
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indirectx = 1'b0;
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indirecty = 1'b0;
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relative = 1'b0;
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relative = 1'b0;
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zero_page = 1'b0;
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zero_page = 1'b0;
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zero_page_indexed = 1'b0;
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zero_page_indexed = 1'b0;
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index = 1'b0;
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index = 1'b0;
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| Line 662... |
Line 722... |
end
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end
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ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
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ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
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absolute_indexed = 1'b1;
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absolute_indexed = 1'b1;
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index = alu_y;
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index = alu_y;
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end
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end
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ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
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ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX: begin
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ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
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indirectx = 1'b1;
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indirect = 1'b1;
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index = alu_x;
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end
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ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY, ORA_IDY, SBC_IDY, STA_IDY: begin
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indirecty = 1'b1;
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index = alu_y;
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end
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end
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default: begin
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default: begin
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$write("state : %b", state);
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$write("state : %b", state);
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if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
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if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
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$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
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$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
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