| Line 7... |
Line 7... |
//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 6507 FSM ////
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//// 6507 FSM ////
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//// ////
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//// ////
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//// TODO: ////
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//// TODO: ////
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//// - Code the indexed indirect mode ////
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//// - Fix relative mode, bit 7 means negative ////
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//// - Code the indirect indexed mode ////
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//// - Code the indirect indexed mode ////
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//// - Code the absolute indirect mode ////
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//// - Code the absolute indirect mode ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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| Line 99... |
Line 99... |
reg [DATA_SIZE_:0] sp; // stack pointer
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reg [DATA_SIZE_:0] sp; // stack pointer
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reg [DATA_SIZE_:0] ir; // instruction register
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reg [DATA_SIZE_:0] ir; // instruction register
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reg [ADDR_SIZE_:0] temp_addr; // temporary address
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reg [ADDR_SIZE_:0] temp_addr; // temporary address
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reg [DATA_SIZE_:0] temp_data; // temporary data
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reg [DATA_SIZE_:0] temp_data; // temporary data
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reg [3:0] state, next_state; // current and next state registers
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reg [4:0] state, next_state; // current and next state registers
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// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
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// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
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// wiring that simplifies the FSM logic
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// wiring that simplifies the FSM logic
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reg absolute;
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reg absolute;
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reg absolute_indexed;
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reg absolute_indexed;
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| Line 144... |
Line 144... |
{page_crossed, address_plus_index[7:0]} = pc[7:0] + index;
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{page_crossed, address_plus_index[7:0]} = pc[7:0] + index;
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address_plus_index[12:8] = pc[12:8] + page_crossed;// warning: pc might feed these lines twice and cause branch failure
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address_plus_index[12:8] = pc[12:8] + page_crossed;// warning: pc might feed these lines twice and cause branch failure
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end // solution: add a temp reg i guess
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end // solution: add a temp reg i guess
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end
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end
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else if (state == READ_FROM_POINTER) begin
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else if (state == READ_FROM_POINTER) begin
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if (indirectx) begin
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{page_crossed, address_plus_index[7:0]} = temp_data + index;
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{page_crossed, address_plus_index[7:0]} = temp_data + index;
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address_plus_index[12:8] = 5'b00000;
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address_plus_index[12:8] = 5'b00000;
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end
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end
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else begin // indirecty falls here
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address_plus_index[7:0] = temp_data + 8'h01;
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address_plus_index[12:8] = 5'b00000;
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end
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end
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else if (state == READ_FROM_POINTER_X) begin
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else if (state == READ_FROM_POINTER_X) begin
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{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;
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{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;
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address_plus_index[12:8] = 5'b00000;
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address_plus_index[12:8] = 5'b00000;
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end
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end
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else if (state == READ_FROM_POINTER_X1) begin
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{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
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address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
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end
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end
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end
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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// all registers must assume default values
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// all registers must assume default values
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| Line 226... |
Line 236... |
pc <= next_pc;
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pc <= next_pc;
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address <= {{5{1'b0}}, data_in};
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address <= {{5{1'b0}}, data_in};
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temp_addr <= {{5{1'b0}}, data_in};
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temp_addr <= {{5{1'b0}}, data_in};
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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else if (indirectx) begin
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else if (indirectx || indirecty) begin
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pc <= next_pc;
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pc <= next_pc;
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address <= data_in;
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address <= data_in;
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temp_data <= data_in;
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temp_data <= data_in;
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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| Line 368... |
Line 378... |
control <= MEM_READ;
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control <= MEM_READ;
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data_out <= 8'h00;
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data_out <= 8'h00;
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end
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end
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READ_FROM_POINTER: begin
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READ_FROM_POINTER: begin
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pc <= pc;
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pc <= pc;
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address <= address_plus_index;
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//temp_addr[7:0] <= data_in;
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control <= MEM_READ;
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control <= MEM_READ;
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if (indirectx) begin
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address <= address_plus_index;
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end
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else begin // indirecty falls here
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address <= address_plus_index;
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temp_addr <= {{5{1'b0}}, data_in};
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end
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end
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end
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READ_FROM_POINTER_X: begin
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READ_FROM_POINTER_X: begin
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pc <= pc;
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pc <= pc;
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address <= address_plus_index;
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address <= address_plus_index;
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temp_addr[7:0] <= data_in;
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temp_addr[7:0] <= data_in;
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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READ_FROM_POINTER_X1: begin
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READ_FROM_POINTER_X1: begin
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pc <= pc;
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pc <= pc;
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if (indirectx) begin
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address <= {data_in[5:0], temp_addr[7:0]};
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address <= {data_in[5:0], temp_addr[7:0]};
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if (write) begin
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if (write) begin
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control <= MEM_WRITE;
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control <= MEM_WRITE;
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data_out <= alu_result;
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end
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end
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else begin
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else begin
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control <= MEM_READ;
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control <= MEM_READ;
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end
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end
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end
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end
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else begin // indirecty falls here
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address <= address_plus_index;
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temp_addr[12:8] <= data_in;
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control <= MEM_READ;
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end
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end
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default: begin
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default: begin
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
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$finish(0);
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$finish(0);
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end
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end
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| Line 463... |
Line 488... |
next_state = FETCH_HIGH_CALC_INDEX;
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next_state = FETCH_HIGH_CALC_INDEX;
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end
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end
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else if (relative) begin
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else if (relative) begin
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next_state = FETCH_OP_EVAL_BRANCH;
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next_state = FETCH_OP_EVAL_BRANCH;
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end
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end
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else if (indirectx) begin
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else if (indirectx || indirecty) begin
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next_state = READ_FROM_POINTER;
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next_state = READ_FROM_POINTER;
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end
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end
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end
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end
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READ_FROM_POINTER: begin
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READ_FROM_POINTER: begin
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if (indirectx) begin
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next_state = READ_FROM_POINTER_X;
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next_state = READ_FROM_POINTER_X;
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end
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end
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else begin // indirecty falls here
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next_state = READ_FROM_POINTER_X1;
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end
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end
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READ_FROM_POINTER_X: begin
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READ_FROM_POINTER_X: begin
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next_state = READ_FROM_POINTER_X1;
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next_state = READ_FROM_POINTER_X1;
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end
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end
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READ_FROM_POINTER_X1: begin
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READ_FROM_POINTER_X1: begin
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if (indirecty) begin
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next_state = READ_MEM_FIX_ADDR;
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end
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else begin
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if (read || read_modify_write) begin
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if (read || read_modify_write) begin
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next_state = READ_MEM;
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next_state = READ_MEM;
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end
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end
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else if (write) begin
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else if (write) begin
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alu_opcode = ir;
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alu_opcode = ir;
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alu_enable = 1'b1;
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alu_enable = 1'b1;
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next_state = WRITE_MEM;
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next_state = WRITE_MEM;
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end
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end
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end
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end
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end
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FETCH_OP_EVAL_BRANCH: begin
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FETCH_OP_EVAL_BRANCH: begin
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if (branch) begin
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if (branch) begin
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next_state = FETCH_OP_FIX_PC;
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next_state = FETCH_OP_FIX_PC;
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end
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end
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else begin
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else begin
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