URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 98 and 100
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 98 |
Rev 100 |
| Line 164... |
Line 164... |
/* testing IDY mode READ TYPE, page crossed.
|
/* testing IDY mode READ TYPE, page crossed.
|
address may assume a invalid value when page is crossed but it is fixed on the next cycle when the true read occurs.
|
address may assume a invalid value when page is crossed but it is fixed on the next cycle when the true read occurs.
|
this is probably not an issue */
|
this is probably not an issue */
|
fake_mem[331] = LDA_IDY;
|
fake_mem[331] = LDA_IDY;
|
fake_mem[332] = 8'hfe;
|
fake_mem[332] = 8'hfe;
|
// FALTOU O WRITE INDIRETO Y!
|
fake_mem[333] = STA_IDY;
|
|
fake_mem[334] = 8'h00; // testing IDY mode WRITE TYPE, page not crossed;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
@(negedge clk) // will wait for next negative edge of the clock (t=20)
|
@(negedge clk) // will wait for next negative edge of the clock (t=20)
|
reset_n=1'b1;
|
reset_n=1'b1;
|
|
|
|
|
#3000;
|
#3000;
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.