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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 98 and 100
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| Rev 98 |
Rev 100 |
| Line 164... |
Line 164... |
/* testing IDY mode READ TYPE, page crossed.
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/* testing IDY mode READ TYPE, page crossed.
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address may assume a invalid value when page is crossed but it is fixed on the next cycle when the true read occurs.
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address may assume a invalid value when page is crossed but it is fixed on the next cycle when the true read occurs.
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this is probably not an issue */
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this is probably not an issue */
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fake_mem[331] = LDA_IDY;
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fake_mem[331] = LDA_IDY;
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fake_mem[332] = 8'hfe;
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fake_mem[332] = 8'hfe;
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// FALTOU O WRITE INDIRETO Y!
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fake_mem[333] = STA_IDY;
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fake_mem[334] = 8'h00; // testing IDY mode WRITE TYPE, page not crossed;
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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reset_n=1'b1;
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reset_n=1'b1;
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#3000;
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#3000;
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