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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 101 and 102
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| Rev 101 |
Rev 102 |
| Line 169... |
Line 169... |
fake_mem[332] = 8'hfe;
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fake_mem[332] = 8'hfe;
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fake_mem[333] = STA_IDY; // testing IDY mode WRITE TYPE, page crossed;
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fake_mem[333] = STA_IDY; // testing IDY mode WRITE TYPE, page crossed;
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fake_mem[334] = 8'h00;
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fake_mem[334] = 8'h00;
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fake_mem[335] = STA_IDY; // testing IDY mode WRITE TYPE, page not crossed;
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fake_mem[335] = STA_IDY; // testing IDY mode WRITE TYPE, page not crossed;
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fake_mem[336] = 8'h0e;
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fake_mem[336] = 8'h0e;
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fake_mem[337] = JMP_IND; // testing absolute indirect addressing. page crossed when updating pointer.
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fake_mem[337] = INX_IMP;
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fake_mem[338] = 8'hff;
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fake_mem[338] = JMP_IND; // testing absolute indirect addressing. page crossed when updating pointer.
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fake_mem[339] = 8'h00;
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fake_mem[339] = 8'hff;
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fake_mem[340] = 8'h00;
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//fake_mem[337] = JMP_IND; // testing absolute indirect addressing. no page crossed when updating pointer.
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//fake_mem[337] = JMP_IND; // testing absolute indirect addressing. no page crossed when updating pointer.
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//fake_mem[338] = 8'h3b;
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//fake_mem[338] = 8'h3b;
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//fake_mem[339] = 8'h00;
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//fake_mem[339] = 8'h00;
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| Line 185... |
Line 186... |
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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reset_n=1'b1;
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reset_n=1'b1;
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#3000;
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#4000;
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$finish; // to shut down the simulation
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$finish; // to shut down the simulation
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end //initial
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end //initial
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always @(clk) begin
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always @(clk) begin
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if (control == 0) begin // MEM_READ
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if (control == 0) begin // MEM_READ
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