URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 110 and 111

Rev 110	Rev 111
Line 62...	Line 62...
`wire [7:0] data_out;`	`wire [7:0] data_out;`
`wire [7:0] alu_opcode;`	`wire [7:0] alu_opcode;`
`wire [7:0] alu_a;`	`wire [7:0] alu_a;`
`wire alu_enable;`	`wire alu_enable;`

`integer i;`	`integer my_i;`

`include "../T6507LP_Package.v" // TODO: remove this include	`include "../T6507LP_Package.v" // TODO: remove this include

`t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);`	`t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);`

Line 80...	Line 80...
`alu_result = 8'h01;`	`alu_result = 8'h01;`
`alu_status = 8'h00;`	`alu_status = 8'h00;`
`alu_x = 8'h07;`	`alu_x = 8'h07;`
`alu_y = 8'h03;`	`alu_y = 8'h03;`

`for (i=0; i < 2**13; i= i+1) begin`	`for (my_i=0; my_i < 2**13; my_i= my_i+1) begin`
`$write("\n%d",i);`	`$write("\n%d",my_i);`
`fake_mem[i]=8'h00;`	`fake_mem[my_i]=8'h00;`
`end`	`end`


`fake_mem[0] = ASL_ACC; // testing ACC mode`	`fake_mem[0] = ASL_ACC; // testing ACC mode`
`fake_mem[1] = ADC_IMM; // testing IMM mode`	`fake_mem[1] = ADC_IMM; // testing IMM mode`