URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 111 and 112

Rev 111	Rev 112
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`//// Public License along with this source; if not, download it ////`	`//// Public License along with this source; if not, download it ////`
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`////////////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////////////`

	`include "timescale.v"
`timescale 1ns / 1ps

`module t6507lp_fsm_tb();`	`module t6507lp_fsm_tb();`
`reg clk;`	`reg clk;`
`reg reset_n;`	`reg reset_n;`
`reg [7:0] alu_result;`	`reg [7:0] alu_result;`
Line 64...	Line 63...
`wire [7:0] alu_a;`	`wire [7:0] alu_a;`
`wire alu_enable;`	`wire alu_enable;`

`integer my_i;`	`integer my_i;`

`include "../T6507LP_Package.v" // TODO: remove this include	`include "T6507LP_Package.v" // TODO: remove this include

`t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);`	`t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);`

`always #10 clk = ~clk;`	`always #10 clk = ~clk;`