| Line 6... |
Line 6... |
//// http://www.opencores.org/cores/t6507lp/ ////
|
//// http://www.opencores.org/cores/t6507lp/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// 6507 FSM testbench ////
|
//// 6507 FSM testbench ////
|
//// ////
|
//// ////
|
//// TODO: ////
|
|
//// - Test indirect indexed mode ////
|
|
//// - Test absolute indirect mode ////
|
|
//// - Test special stack instructions ////
|
|
//// ////
|
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
|
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
|
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
|
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////
|
| Line 45... |
Line 40... |
////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////
|
|
|
`include "timescale.v"
|
`include "timescale.v"
|
|
|
module t6507lp_fsm_tb();
|
module t6507lp_fsm_tb();
|
|
// mem_rw signals
|
|
localparam MEM_READ = 1'b0;
|
|
localparam MEM_WRITE = 1'b1;
|
|
|
reg clk;
|
reg clk;
|
reg reset_n;
|
reg reset_n;
|
reg [7:0] alu_result;
|
reg [7:0] alu_result;
|
reg [7:0] alu_status;
|
reg [7:0] alu_status;
|
reg [7:0] data_in;
|
reg [7:0] data_in;
|
|
|
reg [7:0] alu_x;
|
reg [7:0] alu_x;
|
reg [7:0] alu_y;
|
reg [7:0] alu_y;
|
|
|
wire [12:0] address;
|
wire [12:0] address;
|
wire control;
|
wire mem_rw;
|
wire [7:0] data_out;
|
wire [7:0] data_out;
|
wire [7:0] alu_opcode;
|
wire [7:0] alu_opcode;
|
wire [7:0] alu_a;
|
wire [7:0] alu_a;
|
wire alu_enable;
|
wire alu_enable;
|
|
|
integer my_i;
|
integer my_i;
|
|
|
`include "T6507LP_Package.v" // TODO: remove this include
|
`include "T6507LP_Package.v"
|
|
|
t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
|
t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, mem_rw, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
|
|
|
always #10 clk = ~clk;
|
always #10 clk = ~clk;
|
|
|
reg[7:0] fake_mem[2**13-1:0];
|
reg[7:0] fake_mem[2**13-1:0];
|
|
|
| Line 202... |
Line 201... |
#4000;
|
#4000;
|
$finish; // to shut down the simulation
|
$finish; // to shut down the simulation
|
end //initial
|
end //initial
|
|
|
always @(clk) begin
|
always @(clk) begin
|
if (control == 0) begin // MEM_READ
|
if (mem_rw == MEM_READ) begin // MEM_READ
|
data_in <= fake_mem[address];
|
data_in <= fake_mem[address];
|
$write("\nreading from mem position %h: %h", address, fake_mem[address]);
|
$write("\nreading from mem position %h: %h", address, fake_mem[address]);
|
end
|
end
|
else if (control == 1'b1) begin // MEM_WRITE
|
else begin // MEM_WRITE
|
fake_mem[address] <= data_out;
|
fake_mem[address] <= data_out;
|
$write("\nreading from mem position %h: %h", address, fake_mem[address]);
|
$write("\nreading from mem position %h: %h", address, fake_mem[address]);
|
end
|
end
|
end
|
end
|
|
|
