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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 116 and 117
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| Rev 116 |
Rev 117 |
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Line 44... |
module t6507lp_fsm_tb();
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module t6507lp_fsm_tb();
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// mem_rw signals
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// mem_rw signals
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localparam MEM_READ = 1'b0;
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localparam MEM_READ = 1'b0;
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localparam MEM_WRITE = 1'b1;
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localparam MEM_WRITE = 1'b1;
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reg clk;
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reg clk; // regs are inputs
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reg reset_n;
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reg reset_n;
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reg [7:0] alu_result;
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reg [7:0] alu_result;
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reg [7:0] alu_status;
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reg [7:0] alu_status;
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reg [7:0] data_in;
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reg [7:0] data_in;
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reg [7:0] alu_x;
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reg [7:0] alu_x;
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reg [7:0] alu_y;
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reg [7:0] alu_y;
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wire [12:0] address; // wires are outputs
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wire [12:0] address;
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wire mem_rw;
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wire mem_rw;
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wire [7:0] data_out;
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wire [7:0] data_out;
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wire [7:0] alu_opcode;
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wire [7:0] alu_opcode;
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wire [7:0] alu_a;
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wire [7:0] alu_a;
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wire alu_enable;
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wire alu_enable;
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integer my_i;
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integer my_i;
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`include "T6507LP_Package.v"
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`include "T6507LP_Package.v"
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t6507lp_fsm #(8,13) my_dut(
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t6507lp_fsm #(8,13) t6507lp_fsm(
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.clk(clk),
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.clk(clk),
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.reset_n(reset_n),
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.reset_n(reset_n),
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.alu_result(alu_result),
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.alu_result(alu_result),
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.alu_status(alu_status),
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.alu_status(alu_status),
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.data_in(data_in),
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.data_in(data_in),
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.alu_x(alu_x),
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.alu_y(alu_y),
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.address(address),
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.address(address),
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.mem_rw(mem_rw),
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.mem_rw(mem_rw),
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.data_out(data_out),
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.data_out(data_out),
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.alu_opcode(alu_opcode),
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.alu_opcode(alu_opcode),
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.alu_a(alu_a),
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.alu_a(alu_a),
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.alu_enable(alu_enable),
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.alu_enable(alu_enable)
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.alu_x(alu_x),
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.alu_y(alu_y)
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);
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);
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always #10 clk = ~clk;
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always #10 clk = ~clk;
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reg[7:0] fake_mem[2**13-1:0];
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reg[7:0] fake_mem[2**13-1:0];
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initial begin
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initial begin
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clk = 0;
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clk = 1'b0;
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reset_n = 1'b0;
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reset_n = 1'b0;
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alu_result = 8'h01;
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alu_result = 8'h01;
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alu_status = 8'h00;
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alu_status = 8'h00;
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alu_x = 8'h07;
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alu_x = 8'h07;
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alu_y = 8'h03;
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alu_y = 8'h03;
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| Line 97... |
Line 95... |
for (my_i=0; my_i < 2**13; my_i= my_i+1) begin
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for (my_i=0; my_i < 2**13; my_i= my_i+1) begin
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$write("\n%d",my_i);
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$write("\n%d",my_i);
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fake_mem[my_i]=8'h00;
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fake_mem[my_i]=8'h00;
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end
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end
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fake_mem[0] = ASL_ACC; // testing ACC mode
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fake_mem[0] = ASL_ACC; // testing ACC mode
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fake_mem[1] = ADC_IMM; // testing IMM mode
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fake_mem[1] = ADC_IMM; // testing IMM mode
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fake_mem[2] = 8'h27;
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fake_mem[2] = 8'h27;
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fake_mem[3] = JMP_ABS; // testing ABS mode, JMP type
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fake_mem[3] = JMP_ABS; // testing ABS mode, JMP type
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fake_mem[4] = 8'h09;
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fake_mem[4] = 8'h09;
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