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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 67 and 68

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Rev 67	Rev 68
Line 45...	Line 45...

`timescale 1ns / 1ps	`timescale 1ns / 1ps

`module t6507lp_fsm_tb();`	`module t6507lp_fsm_tb();`
`reg clk_in;`	`reg clk_in;`
`reg n_rst_in;`	`reg rst_in_n;`
`reg [7:0] alu_result;`	`reg [7:0] alu_result;`
`reg [7:0] alu_status;`	`reg [7:0] alu_status;`
`reg [7:0] data_in;`	`reg [7:0] data_in;`

`wire [12:0] address;`	`wire [12:0] address;`
Line 59...	Line 59...
`wire [7:0] alu_a;`	`wire [7:0] alu_a;`
`wire alu_enable;`	`wire alu_enable;`

`include "../T6507LP_Package.v"	`include "../T6507LP_Package.v"

`t6507lp_fsm my_dut(clk_in, n_rst_in, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);`	`t6507lp_fsm #(8,13) my_dut(clk_in, rst_in_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);`

`always #10 clk_in = ~clk_in;`	`always #10 clk_in = ~clk_in;`

`initial begin`	`initial begin`
`clk_in = 0;`	`clk_in = 0;`
`data_in = ASL_ACC;`	`data_in = ASL_ACC;`
`n_rst_in = 1'b0;`	`rst_in_n = 1'b0;`
`alu_result = 0;`	`alu_result = 0;`
`alu_status = 0;`	`alu_status = 0;`

`@(negedge clk_in) //will wait for next negative edge of the clock (t=20)`	`@(negedge clk_in) //will wait for next negative edge of the clock (t=20)`
`n_rst_in=1'b1;`	`rst_in_n=1'b1;`

`@(negedge clk_in) //will wait for next negative edge of the clock (t=40)`	`@(negedge clk_in) //will wait for next negative edge of the clock (t=40)`
`data_in = ROL_ACC;`	`data_in = ROL_ACC;`

`@(negedge clk_in) //will wait for next negative edge of the clock (t=60)`	`@(negedge clk_in) //will wait for next negative edge of the clock (t=60)`

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 67 and 68