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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module t6507lp_fsm_tb();
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module t6507lp_fsm_tb();
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reg clk_in;
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reg clk;
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reg rst_in_n;
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reg reset_n;
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reg [7:0] alu_result;
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reg [7:0] alu_result;
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reg [7:0] alu_status;
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reg [7:0] alu_status;
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reg [7:0] data_in;
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reg [7:0] data_in;
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wire [12:0] address;
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wire [12:0] address;
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wire [7:0] alu_a;
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wire [7:0] alu_a;
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wire alu_enable;
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wire alu_enable;
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`include "../T6507LP_Package.v"
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`include "../T6507LP_Package.v"
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t6507lp_fsm #(8,13) my_dut(clk_in, rst_in_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
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t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
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always #10 clk_in = ~clk_in;
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always #10 clk = ~clk;
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reg[7:0] fake_mem[20:0];
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initial begin
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initial begin
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clk_in = 0;
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clk = 0;
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data_in = ASL_ACC;
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reset_n = 1'b0;
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rst_in_n = 1'b0;
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alu_result = 8'h01;
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alu_result = 0;
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alu_status = 0;
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alu_status = 0;
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@(negedge clk_in) //will wait for next negative edge of the clock (t=20)
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fake_mem[0] = ASL_ACC; // testing ACC mode
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rst_in_n=1'b1;
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fake_mem[1] = ADC_IMM; // testing IMM mode
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fake_mem[2] = 8'h27;
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fake_mem[3] = JMP_ABS; // testing ABS mode, JMP type
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fake_mem[4] = 8'h09;
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fake_mem[5] = 8'h00;
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fake_mem[6] = ASL_ACC; // wont be executed
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fake_mem[7] = ASL_ACC; // wont be executed
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fake_mem[8] = ASL_ACC; // wont be executed
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fake_mem[9] = ASL_ACC; // wont be executed
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fake_mem[10] = LDA_ABS; // testing ABS mode, READ type. A = MEM[0002]. (a=27)
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fake_mem[11] = 8'h02;
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fake_mem[12] = 8'h00;
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fake_mem[13] = ASL_ABS; // testing ABS mode, READ_MODIFY_WRITE type. should overwrite the first ASL_ACC
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fake_mem[14] = 8'h04;
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fake_mem[15] = 8'h00;
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fake_mem[16] = 8'h00;
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@(negedge clk_in) //will wait for next negative edge of the clock (t=40)
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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data_in = ROL_ACC;
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reset_n=1'b1;
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@(negedge clk_in) //will wait for next negative edge of the clock (t=60)
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data_in = ROR_ACC;
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@(negedge clk_in) //will wait for next negative edge of the clock (t=80)
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#500;
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@(negedge clk_in) //will wait for next negative edge of the clock (t=100)
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@(negedge clk_in) //will wait for next negative edge of the clock (t=120)
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$finish; // to shut down the simulation
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$finish; // to shut down the simulation
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end //initial
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end //initial
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always @(clk) begin
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if (control == 0) begin // MEM_READ
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data_in <= fake_mem[address];
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$write("\nreading from mem position %h: %h", address, fake_mem[address]);
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end
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else if (control == 1'b1) begin // MEM_WRITE
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fake_mem[address] <= data_out;
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$write("\nreading from mem position %h: %h", address, fake_mem[address]);
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end
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end
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endmodule
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endmodule
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