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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 71 and 76

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Rev 71 Rev 76
Line 63... Line 63... 
 
 
 
 
        t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
 
        t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
 
 
 
 
 
        always #10 clk = ~clk;
 
        always #10 clk = ~clk;
 
 
 
 
 
        reg[7:0] fake_mem[20:0];
 
        reg[7:0] fake_mem[30:0];
 
 
 
 
 
        initial begin
 
        initial begin
 
                clk = 0;
 
                clk = 0;
 
                reset_n = 1'b0;
 
                reset_n = 1'b0;
 
                alu_result = 8'h01;
 
                alu_result = 8'h01;
Line 85... Line 85... 
                fake_mem[9] = ASL_ACC; // wont be executed
 
                fake_mem[9] = ASL_ACC; // wont be executed
 
                fake_mem[10] = LDA_ABS; // testing ABS mode, READ type. A = MEM[0002]. (a=27)
 
                fake_mem[10] = LDA_ABS; // testing ABS mode, READ type. A = MEM[0002]. (a=27)
 
                fake_mem[11] = 8'h02;
 
                fake_mem[11] = 8'h02;
 
                fake_mem[12] = 8'h00;
 
                fake_mem[12] = 8'h00;
 
                fake_mem[13] = ASL_ABS; // testing ABS mode, READ_MODIFY_WRITE type. should overwrite the first ASL_ACC
 
                fake_mem[13] = ASL_ABS; // testing ABS mode, READ_MODIFY_WRITE type. should overwrite the first ASL_ACC
 
                fake_mem[14] = 8'h04;
 
                fake_mem[14] = 8'h00;
 
                fake_mem[15] = 8'h00;
 
                fake_mem[15] = 8'h00;
 
                fake_mem[16] = 8'h00;
 
                fake_mem[16] = STA_ABS; // testing ABS mode, WRITE type. should write alu_result on MEM[1]
 
 
 
                fake_mem[17] = 8'h01;
 
 
 
                fake_mem[18] = 8'h00;
 
 
 
                fake_mem[19] = LDA_ZPG; // testing ZPG mode, READ type
 
 
 
                fake_mem[20] = 8'h00;
 
 
 
                fake_mem[21] = 8'h00;
 
 
 
 
 
                @(negedge clk) // will wait for next negative edge of the clock (t=20)
 
                @(negedge clk) // will wait for next negative edge of the clock (t=20)
 
                reset_n=1'b1;
 
                reset_n=1'b1;
 
 
 
 
 
 
 
 
 
                #500;
 
                #700;
 
                $finish; // to shut down the simulation
 
                $finish; // to shut down the simulation
 
        end //initial
 
        end //initial
 
 
 
 
 
        always @(clk) begin
 
        always @(clk) begin
 
                if (control == 0) begin // MEM_READ
 
                if (control == 0) begin // MEM_READ

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